STM32H723VG datasheet(25/227 Pages) STMICROELECTRONICS

25 / 227 page

DS13313 Rev 2

25/227

STM32H723xE/G

Functional overview

During power-up and power-down phases, the following power sequence requirements

must be respected (see Figure 2):

•

When VDD is below 1 V, other power supplies (VDDA, VDD33USB) must remain below

VDD + 300 mV.

•

When VDD is above 1 V, all power supplies are independent.

During the power-down phase, VDD can temporarily become lower than other supplies only

if the energy provided to the microcontroller remains below 1 mJ. This allows external

decoupling capacitors to be discharged with different time constants during the power-down

transient phase.

Figure 2. Power-up/power-down sequence

1. VDDx refers to any power supply among VDDA, VDD33USB.

3.7.2

Power supply supervisor

The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry

coupled with a Brownout reset (BOR) circuitry:

•

Power-on reset (POR)

The POR supervisor monitors VDD power supply and compares it to a fixed threshold.

The devices remain in Reset mode when VDD is below this threshold,

•

Power-down reset (PDR)

The PDR supervisor monitors VDD power supply. A reset is generated when VDD drops

below a fixed threshold.

The PDR supervisor can be enabled/disabled through PDR_ON pin.

•

Brownout reset (BOR)

The BOR supervisor monitors VDD power supply. Three BOR thresholds (from 2.1 to

2.7 V) can be configured through option bytes. A reset is generated when VDD drops

below this threshold.

MSv47490V1

0.3

VBOR0

3.6

Operating mode

Power-on

Power-down

time

VDDX

(1)

VDD

Invalid supply area

VDDX < VDD + 300 mV

VDDX independent from VDD

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