STM32H723VG datasheet(27/227 Pages) STMICROELECTRONICS

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DS13313 Rev 2

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STM32H723xE/G

Functional overview

3.9

Reset and clock controller (RCC)

The clock and reset controller is located in D3 domain. The RCC manages the generation of

all the clocks, as well as the clock gating and the control of the system and peripheral

resets. It provides a high flexibility in the choice of clock sources and allows to apply clock

ratios to improve the power consumption. In addition, on some communication peripherals

that are capable to work with two different clock domains (either a bus interface clock or a

kernel peripheral clock), thus the system frequency can be changed without modifying the

baudrate.

3.9.1

Clock management

The devices embed four internal oscillators, two oscillators with external crystal or

resonator, two internal oscillators with fast startup time and three PLLs.

The RCC receives the following clock source inputs:

•

Internal oscillators:

–

64 MHz HSI clock

–

48 MHz RC oscillator

–

4 MHz CSI clock

–

32 kHz LSI clock

•

External oscillators:

–

HSE clock: 4-50 MHz (generated from an external source) or 4-48 MHz(generated

from a crystal/ceramic resonator)

–

LSE clock: 32.768 kHz

The RCC provides three PLLs: one for system clock, two for kernel clocks.

The system starts on the HSI clock. The user application can then select the clock

configuration.

Table 2. System versus domain low-power mode

System power mode

D1 domain power mode

D2 domain power mode

D3 domain power mode

Run

DRun/DStop/DStandby

DRun

Stop

DStop/DStandby

DStop

Standby

DStandby

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