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STM32H723VG Datasheet(PDF) 179 Page - STMicroelectronics |
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STM32H723VG Datasheet(HTML) 179 Page - STMicroelectronics |
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179 / 227 page ![]() DS13313 Rev 2 179/227 STM32H723xE/G Electrical characteristics 208 CLOAD Capacitive load - - - 50 pF CMRR Common mode rejection ratio -- 80 - dB PSRR Power supply rejection ratio CLOAD ≤ 50pf / RLOAD ≥ 4 kΩ(2) at 1 kHz, Vcom=VDDA/2 50 66 - dB GBW Gain bandwidth for high supply range 200 mV ≤ Output dynamic range ≤ VDDA - 200 mV 47.3 12.3 MHz SR Slew rate (from 10% and 90% of output voltage) Normal mode - 3 - V/µs High-speed mode - 24 - AO Open loop gain 200 mV ≤ Output dynamic range ≤ VDDA - 200 mV 59 90 129 dB φm Phase margin - - 55 - ° GM Gain margin - - 12 - dB VOHSAT High saturation voltage Iload=max or RLOAD=min, Input at VDDA VDDA −100 mV - - mV VOLSAT Low saturation voltage Iload=max or RLOAD=min, Input at 0 V - - 100 tWAKEUP Wake up time from OFF state Normal mode CLOAD ≤ 50pf, RLOAD ≥ 4 kΩ, follower configuration -0.8 3.2 µs High speed mode CLOAD ≤ 50pf, RLOAD ≥ 4 kΩ, follower configuration -0.9 2.8 PGA gain Non inverting gain error value PGA gain = 2 −1- 1 % PGA gain = 4 −2- 2 PGA gain = 8 −2.5 - 2.5 PGA gain = 16 −3- 3 Inverting gain error value PGA gain = 2 −1- 1 PGA gain = 4 −1- 1 PGA gain = 8 −2- 2 PGA gain = 16 −3- 3 External non-inverting gain error value PGA gain = 2 −1- 1 PGA gain = 4 −3- 3 PGA gain = 8 −3.5 - 3.5 PGA gain = 16 −4- 4 Table 96. Operational amplifier characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit |
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