MCP37D11T-80ESLASHTE datasheet(56/136 Pages) MICROCHIP

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MCP37D11-80: 80 MSPS 12-BIT PIPELINED ADC

DS20006381A-page 56

 2020 Microchip Technology Inc.

4.8.5

EXAMPLES OF REGISTER

SETTINGS FOR USING DDC AND

DECIMATION

The following tables show examples of setting registers

for using decimation and digital down-conversion

(DDC) depending on the output type selection.

TABLE 4-17:

FOR SINGLE-CHANNEL MODE – EXAMPLE

DDC

Mode

Addr.

0x02(2)

FIR A Filter

FIR B Filter

DDC1

DDC2

Dual-Channel

DSPP Control

Output

Disabled

0x00

0,0,0

ADC

Disabled

0x33

0x03

0x00

0,0,0

ADC with decimation

(÷8)

512

Disabled

0x99

0xFF

0x00

0,0,0

ADC with decimation

(÷512)

I/Q

0x00(5)

0x00

1,0,1

0,0,0

I/Q Data

I/Q

0x33

0x07

1,0,1

0,0,0

Decimated I/Q (÷8)

0fS/8

0x11(6)

0x00

1,1,1

0,0,0

Real without

additional decimation

8fS/8

0x44

0x07

1,0,1

1,0,0

Real with decimation

(÷16)

Note 1:

When DDC is used, the actual total decimation is 2x larger since 2x is included from the DDC Half-Band Filter.

Example: Decimation = 8x with DDC-I/Q option actually has 16x decimation with 8x provided by the decimation filter

and 2x from the DDC Half-Band Filter.

Output data and clock rate control register.

0x80<5,1,0> = <EN_NCO, EN_DDC_FS/8, EN_DDC1>.

0x81<6,3,2> = <EN_DDC2, EN_DSPP_8, 8CH_CW>.

Each of I/Q has 1/2 of fS bandwidth. The combined bandwidth is the same as the fS bandwidth. Therefore the data rate

adjustment is not needed.

The Half-Band Filter A includes decimation of 2.

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