MCP37D11T-80ESLASHTE datasheet(89/136 Pages) MICROCHIP

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 2020 Microchip Technology Inc.

DS20006381A-page 89

MCP37D11-80: 80 MSPS 12-BIT PIPELINED ADC

ADDRESS 0X62 – OUTPUT DATA FORMAT AND OUTPUT TEST PATTERN

U-0

R/W-0

R/W-1

R/W-0

—

FCB

DATA_FORMAT

OUTPUT_MODE<1:0>

TEST_PATTERNS<2:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

Unimplemented: Not used.

bit 6

FCB: Factory-controlled bit. This is not for the user. Do not change default setting.

bit 5

DATA_FORMAT: Output data format selection

1 = Offset binary (unsigned)

0 = Two’s complement (Default)

bit 4-3

OUTPUT_MODE<1:0>: Output mode selection(1)

11 = Do not use. Output is undefined

10 = Select DDR LVDS output mode with even bit first(2)(Default)

01 = Select CMOS output mode

00 = Output disabled

bit 2-0

TEST_PATTERNS<2:0>: Test output data pattern selection(3)

111 = Output data is pseudo-random number (PN) sequence(4)

110 = Sync Pattern for LVDS output

Output: '11111111 0000'

101 = Alternating Sequence for LVDS mode

Output: ‘01010101 1010’

100 = Alternating Sequence for CMOS mode

Output: ‘11111111 1111’ alternating with ‘00000000 0000’

011 = Alternating Sequence for CMOS

Output: ‘01010101 0101’ alternating with ‘10101010 1010’

010 = Ramp Pattern: Output (Q0) is incremented by1 LSB per 64 clock cycles(5)

001 = Double Custom Patterns

Output: Alternating custom pattern A (see Addresses 0X74 - 0X75 – Registers 5-29 –5-30)

and custom pattern B (see Address 0X76 - 0X77 – Registers 5-31 – 5-32)(6)

000 = Normal Operation. Output: ADC data (Default)

Note 1:

See Figures 2-1 –2-2 for the timing diagrams.

Rising edge: Q10, Q8, Q6, Q4, Q2, Q0.

Falling edge: Q11, Q9, Q7, Q5, Q3, Q1.

See Section 4.12.12 “Output Test Patterns” for more details.

(a) In LVDS mode: only the active pins (per register settings) are active. Inactive output pins are High Z state.

(b) In CMOS mode: all data output pins (Q11-Q0), output test pins (TP), OVR and WCK pins are active,

even if they are disabled by register settings.

Since the output test pins (TP) can toggle during this test, the output test pins can draw extra current if

they are connected to the supply pin or ground. To avoid the extra current draws, always leave the TP

pins floating (not connected).

Pseudo-random number (PN) code is generated by the linear feedback shift register (LFSR). See

Section 4.12.12.1, "Pseudo-Random Number (PN) Sequence Output" for more details.

OVR and WCK bits are incremented by 1 per 219 and 218 clock cycles, respectively.

Pattern A<11:0> and B<11:0> are applied to Q<11:0>. Q11 = OVR, Q10 = WCK.

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