AM79C978AVCW datasheet(33/256 Pages) AMD

33 / 256 page

Am79C978A

it is a single function device. AD[31:11] are “don't

cares.” See Table 7.

Table 7.

Slave Configuration Transfers

The active bytes within a DWord are determined by the

byte enable signals. Eight-bit, 16-bit, and 32-bit trans-

fers are supported. DEVSEL is asserted two clock cy-

cles a f t e r t h e h o st h a s a sse r t ed FR AM E . A ll

co nf ig ura t io n cycle s a r e of f i xe d len g t h . The

Am79C978A controller will assert TRDY on the third

clock of the data phase.

The Am79C978A controller does not support burst

transfers for access to configuration space. When the

host keeps FRAME asserted for a second data phase,

the Am79C978A controller will disconnect the transfer.

When the host tries to access the PCI configuration

space while the automatic read of the EEPROM after

H_RESET (see section on RESET) is on-going, the

Am79C978A controller will terminate the access on the

PCI bus with a disconnect/retry response.

The Am79C978A controller supports fast back-to-back

transactions to different targets. This is indicated by the

Fast Back-To-Back Capable bit (PCI Status register, bit

7), which is hardwired to 1. The Am79C978A controller

is capable of detecting a configuration cycle even when

its address phase immediately follows the data phase

of a transaction to a different target without any idle

state in-between. There will be no contention on the

DEVSEL , TR DY, and STOP sign als, since th e

Am79C978A controller asserts DEVSEL on the second

clock after FRAME is asserted (medium timing).

Slave I/O Transfers

After the Am79C978A controller is configured as

an I/O device by setting IOEN (for regular I/O

mode) or MEMEN (for memory mapped I/O mode)

in the PCI Command register, it starts monitoring

the PCI bus for access to its CSR, BCR, or EE-

PROM lo cations. If configured for re gu lar I/ O

mode, the Am79C978A controller will look for an

address that falls within its 32 bytes of I/O address

space (starting from the I/O base address). The

Am79C978A controller asserts DEVSEL if it de-

tects an address match and the access is an I/O

cycle. If configured for memory mapped I/O mode,

the Am79C978A controller will look for an address

that falls within its 32 bytes of memory address

space (starting from the memory mapped I/O base

address). The Am79 C9 78 A contro ller asser ts

DEVSEL if it detects an address match and the ac-

cess is a memory cycle. DEVSEL is asserted two

clock cycles after the host has asserted FRAME.

See Figure 3 and Figure 4.

The Am79C978A controller will not assert DEVSEL if

it detects an address match and the PCI command is

not of the correct type. In memory mapped I/O mode,

the Am79C978A controller aliases all accesses to the

I/O resources of the command types Memory Read

Multiple and Memory Read Line to the basic Memory

Read command. All accesses of the type Memory

Write and Invalidate are aliased to the basic Memory

Write command. Eight-bit, 16-bit, and 32-bit non-

burst transactions are supported. The Am79C978A

controller decodes all 32 address lines to determine

which I/O resource is accessed.

The typical number of wait states added to a slave I/O

or memory mapped I/O read or write access on the part

of the Am79C978A controller is six to seven clock cy-

cles, depending upon the relative phases of the internal

Buffer Management Unit clock and the CLK signal,

since the internal Buffer Management Unit clock is a

divide-by-two version of the CLK signal.

The Am79C978A controller does not support burst

transfers for access to its I/O resources. When the host

keeps FRAME asserted for a second data phase, the

Am79C978A controller will disconnect the transfer.

The Am79C978A controller supports fast back-to-back

transactions to different targets. This is indicated by

the Fast Back-To-Back Capable bit (PCI Status regis-

ter, bit 7), which is hardwired to 1. The Am79C978A

controller is capable of detecting an I/O or a memory-

mapped I/O cycle even when its address phase imme-

diately follows the data phase of a transaction to a

different target, without any idle state in-between.

There will be no contention on the DEVSEL, TRDY,

and STOP signals, since the Am79C978A controller

asserts DEVSEL on the second clock after FRAME is

asserted (medium timing). See Figure 5 and Figure 6.

AD31

AD11

AD10

AD8

AD7

AD2

AD1

AD0

Don’t care

DWord

Index

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