AM79C978AVCW datasheet(41/256 Pages) AMD

41 / 256 page

Am79C978A

Figure 15.

Burst Read Transfer (EXTREQ = 0, MEMCMD = 0)

Basic Non-Burst Write Transfer

By default, the Am79C978A controller uses non-

burst cycles in all bus master write operations. All

controller non-burst write accesses are of the PCI

command type Memory Write (type 7). The byte en-

able signals indicate the byte lanes that have valid

data. The Am79C978A controller typically performs

more than one non-burst write transaction within a

single bus mastership period. FRAME is dropped

between consecutive non-burst write cycles. REQ

stays asserted until FRAME is asserted for the last

transaction. The Am79C978A controller supports

zero wait state write cycles except with descriptor

write transfers. (See the Descriptor DMA Transfers

section for the only exception.) It asserts IRDY im-

mediately after the address phase.

Figure 16 shows two non-burst write transactions.

The first transaction has two wait states. The target

inserts one wait state by asserting DEVSEL one

clock late and another wait state by also asserting

TRDY on e clock la te. The se co nd tra nsaction

shows a zero wait state write cycle. The target as-

serts DEVSEL and TRDY in the same cycle as the

Am79C978A controller asserts IRDY.

Basic Burst Write Transfer

The Am79C978A controller supports burst mode for all

bus master write operations. The burst mode must be

enabled by setting BWRITE (BCR18, bit 5). To allow

burst transfers in descriptor write operations, the

Am79C978A controller must also be programmed to

use SWSTYLE 3 (BCR20, bits 7-0). All controller burst

write transfers are of the PCI command type Memory

Write (type 7). AD[1:0] will both be 0 during the address

phase indicating a linear burst order. The byte enable

signals indicate the byte lanes that have valid data.

The Am79C978A controller will always perform a sin-

gle burst write transaction per bus mastership period,

where transaction is defined as one address phase and

one or multiple data phases. The Am79C978A control-

ler supports zero wait state write cycles except with the

case of descriptor write transfers. (See the Descriptor

DMA Transfers section for the only exception.) The de-

vice asserts IRDY immediately after the address phase

and at the same time star ts sampling DEVSEL.

FRAME is deasserted when the next to last data phase

is completed.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

ADDR

0000

1110

PAR

2345678

DATA

PAR

22399A-18

AM79C978AVCW Datasheet(PDF) 41 Page - Advanced Micro Devices

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