AM79C978AVCW datasheet(81/256 Pages) AMD

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Am79C978A

Table 18.

MII Control Frame Format

The start field (ST) is followed by the operation field (OP).

The operation field (OP) indicates whether the operation

is a read or a write operation. This is followed by the PHY

address (PHYAD) and the register address (REGAD) that

was programed into BCR33 of the Fast Ethernet control-

ler. This field is followed by a bus turnaround field (TA).

During the read operation, the bus turnaround field is

used to determine if the PHY is responding properly to the

read request. The data field to/from the MAC controller is

then written to or read from BCR34. The final field is the

idle field, and it is required to allow the drivers to turn off.

The PHYADD field, which is five bits wide, allows 32

unique PHY addresses. The managed PHY layer device

that is connected to a station management entity via the

MII interface has to respond to transactions addressed to

the PHY’s address. A station management entity at-

tached to multiple PHYs is required to have prior knowl-

edge of the appropriate PHY address.

No SRAM Configuration

If the SRAM_SIZE (BCR25, bits 7-0) value is 0 in the

SRAM size register, the controller will assume that there

is no SRAM present and will reconfigure the four internal

FIFOs into two FIFOs, one for transmit and one for re-

ceive. The FIFOs will operate the same as in the PCnet-

PCI II controller. When the SRAM_SIZE (BCR25, bits 7-

0) value is 0, the SRAM_BND (BCR26, bits 7-0) are ig-

nored by the controller. See Figure 44.

Low Latency Receive Configuration

If the LOLATRX (BCR27, bit 4) bit is set to 1, then the con-

troller will configure itself for a low latency receive config-

uration. In this mode, SRAM is required at all times. If the

SRAM_SIZE (BCR25, bits 7-0) value is 0, the controller

will not configure for low latency receive mode. The con-

troller will provide a fast path on the receive side bypass-

ing the SRAM. All transmit traffic will go to the SRAM, so

SRAM_BND (BCR26, bits 7-0) has no meaning in low la-

tency receive mode. When the controller has received 16

bytes from the network, it will start a DMA request to the

PCI Bus Interface Unit. The controller will not wait for the

first 64 bytes to pass to check for collisions in Low Latency

Receive mode. The controller must be in STOP before

switching to this mode. See Figure 45.

CAUTION: To provide data integrity when switching into

and out of the low latency mode, DO NOT SET the

FASTSPNDE bit when setting the SPND bit. Receive

frames WILL be overwritten and the controller may give

erratic behavior when it is enabled again.

Direct SRAM Access

The SRAM can be accessed through the Expansion Bus

Data port (BCR30). To access this data port, the user

must load the upper address EPADDRU (BCR29, bits 3-

0) and set FLASH (BCR29, bit 15) to 0. Then the user will

load the lower 16 bits of address EPADDRL (BCR28, bits

15-0). To initiate a read, the user reads the Expansion Bus

Data Port (BCR30). This slave access from the PCI will

result in a retry for the very first access. Subsequent ac-

cesses may give a retry or not, depending on whether or

not the data is present and valid. The direct SRAM access

uses the same FLASH/EPROM access except for ac-

cessing the SRAM in word format instead of byte format.

This access is meant to be a diagnostic access only. The

SRAM can only be accessed while the controller is in

STOP or SPND (FASTSPNDE is set to 0) mode.

PRE

PHYAD

REGAD

DATA

IDLE

READ

1.1

AAAAA

RRRRR

D31………D0

WRITE

1.1

AAAAA

RRRRR

D31………D0

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