PIC16F684-ESLASHST datasheet(29/164 Pages) MICROCHIP

29 / 164 page

 2004 Microchip Technology Inc.

Preliminary

DS41202C-page 27

PIC16F684

3.7

Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) is designed to

allow the device to continue to operate in the event of

an oscillator failure. The FSCM can detect oscillator

failure at any point after the device has exited a Reset

or Sleep condition and the Oscillator Start-up Timer

(OST) has expired.

FIGURE 3-8:

FSCM BLOCK DIAGRAM

The FSCM function is enabled by setting the FCMEN

bit in the Configuration Word register (CONFIG). It is

applicable to all external clock options (LP, XT, HS, EC,

RC or IO modes).

In the event of an external clock failure, the FSCM will

set the OSFIF bit (PIR1<2>) and generate an oscillator

fail interrupt if the OSFIE bit (PIE1<2>) is set. The

device will then switch the system clock to the internal

oscillator. The system clock will continue to come from

the internal oscillator unless the external clock recovers

and the Fail-Safe condition is exited.

The frequency of the internal oscillator will depend

upon

the

value

contained

the

IRCF

bits

(OSCCON<6:4>).

Upon

entering

the

Fail-Safe

condition, the OSTS bit (OSCCON<3>) is automati-

cally cleared to reflect that the internal oscillator is

active and the WDT is cleared. The SCS bit

(OSCCON<0>) is not updated. Enabling FSCM does

not affect the LTS bit.

The FSCM sample clock is generated by dividing the

INTRC clock by 64. This will allow enough time

between FSCM sample clocks for a system clock edge

to occur. Figure 3-8 shows the FSCM block diagram.

On the rising edge of the sample clock, the monitoring

latch (CM = 0) will be cleared. On a falling edge of the

primary system clock, the monitoring latch will be set

(CM = 1). In the event that a falling edge of the sample

clock occurs, and the monitoring latch is not set, a clock

failure has been detected. The assigned internal

oscillator is enabled when FSCM is enabled, as

reflected by the IRCF.

3.7.1

FAIL-SAFE CONDITION CLEARING

The

Fail-Safe condition is cleared after a Reset, the

execution of a SLEEP instruction, or a modification of

the SCS bit. While in Fail-Safe condition, the

PIC16F684 uses the internal oscillator as the system

clock source. The IRCF bits (OSCCON<6:4>) can be

modified to adjust the internal oscillator frequency

without exiting the Fail-Safe condition.

The Fail-Safe condition must be cleared before the

OSFIF flag can be cleared.

Primary

LFINTOSC

÷ 64

31 kHz

(~32

µs)

488 Hz

(~2 ms)

Clock Monitor

Latch (CM)

(edge-triggered)

Clock

Failure

Detected

Oscillator

Clock

Note:

Two-Speed

Start-up

automatically

enabled when the Fail-Safe Clock Monitor

mode is enabled.

Note:

Primary clocks with a frequency

≤ ~488 Hz

will be considered failed by the FSCM. A

slow starting oscillator can cause an

FSCM interrupt.

PIC16F684-E/ST Datasheet(PDF) 29 Page - Microchip Technology

PIC16F684-E/ST Datasheet(HTML) 29 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL