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PIC16F684-E/ST Datasheet(PDF) 11 Page - Microchip Technology |
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PIC16F684-E/ST Datasheet(HTML) 11 Page - Microchip Technology |
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11 / 164 page  2004 Microchip Technology Inc. Preliminary DS41202C-page 9 PIC16F684 TABLE 2-1: PIC16F684 SPECIAL REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOD Page Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 99 01h TMR0 Timer0 Module’s register xxxx xxxx 45, 99 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 17, 99 03h STATUS IRP(1) RP1(1) RP0 TO PD Z DC C 0001 1xxx 11, 99 04h FSR Indirect Data Memory Address Pointer xxxx xxxx 17, 99 05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx 31, 99 06h — Unimplemented — — 07h PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx 40, 99 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 17, 99 0Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 13, 99 0Ch PIR1 EEIF ADIF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF 0000 0000 15, 99 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 49, 99 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 49, 99 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 51, 99 11h TMR2 Timer2 Module register 0000 0000 53, 99 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 53, 99 13h CCPR1L Capture/Compare/PWM Register 1 Low Byte XXXX XXXX 75, 99 14h CCPR1H Capture/Compare/PWM Register 1 High Byte XXXX XXXX 75, 99 15h CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 75, 99 16h PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 85, 99 17h ECCPAS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 86, 99 18h WDTCON — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 106, 99 19h CMCON0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 55, 99 1Ah CMCON1 — — — — — — T1GSS C2SYNC ---- --10 59, 99 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx 65, 99 1Fh ADCON0 ADFM VCFG — CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 66, 99 Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear. |
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