| Electronic Components Datasheet Search |
|
PIC16F684-E/ST Datasheet(PDF) 80 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
PIC16F684-E/ST Datasheet(HTML) 80 Page - Microchip Technology |
|
80 / 164 page ![]() PIC16F684 DS41202C-page 78 Preliminary 2004 Microchip Technology Inc. 11.3 Enhanced PWM Mode The Enhanced CCP module produces up to a 10-bit resolution PWM output and may have up to four outputs, depending on the selected operating mode. These outputs, designated P1A through P1D, are multiplexed with I/O pins on PORTC. The pin assignments are summarized in Table 11-3. Figure 11-3 shows a simplified block diagram of PWM operation. To configure I/O pins as PWM outputs, the proper PWM mode must be selected by setting the P1M<1:0> and CCP1M<3:0> bits (CCP1CON<7:6> and CCP1CON<3:0>, respectively). The appropriate TRISC bits must also be set as outputs. FIGURE 11-3: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE 11.3.1 PWM OUTPUT CONFIGURATIONS The P1M<1:0> bits in the CCP1CON register allows one of four configurations: • Single Output • Half-bridge Output • Full-bridge Output, Forward mode • Full-bridge Output, Reverse mode The general relationship of the outputs in all configurations is summarized in Figure 11-3. TABLE 11-3: PIN ASSIGNMENTS FOR VARIOUS ENHANCED CCP MODES CCPR1L CCPR1H (Slave) Comparator TMR2 Comparator PR2 (1) RQ S Duty Cycle Registers CCP1CON<5:4> Clear Timer2, toggle PWM pin and latch duty cycle Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base. TRISC<5> RC5/CCP1/P1A TRISC<4> RC4/C2OUT/P1B TRISC<3> RC3/AN7/P1C TRISC<2> RC2/AN6/P1D Output Controller P1M<1:0> 2 CCP1M<3:0> 4 PWM1CON CCP1/P1A P1B P1C P1D Note: Clearing the CCP1CON register will force the PWM output latches to their default inactive levels. This is not the PORTC I/O data latch. ECCP Mode CCP1CON Configuration RC5 RC4 RC3 RC2 Compatible CCP 00xx11xx CCP1 RC4/C2OUT RC3/AN7 RC2/AN6 Dual PWM 10xx11xx P1A P1B RC3/AN7 RC2/AN6 Quad PWM x1xx11xx P1A P1B P1C P1D Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP in a given mode. Note 1: TRIS register values must be configured appropriately. 2: With ECCP in Dual or Quad PWM mode, the C2OUT output control of PORTC must be disabled. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |