PIC16F684-ESLASHST datasheet(61/164 Pages) MICROCHIP

61 / 164 page

 2004 Microchip Technology Inc.

Preliminary

DS41202C-page 59

PIC16F684

CMCON1 – COMPARATOR CONFIGURATION REGISTER (ADDRESS: 1Ah)

8.4

Comparator Outputs

The comparator outputs are read through the

CMCON0 register. These bits are read-only. The

comparator outputs may also be directly output to the

RA2 and RC4 I/O pins. When enabled, multiplexers in

the output path of the RA2 and RC4 pins will switch

and the output of each pin will be the unsynchronized

output of the comparator. The uncertainty of each of

the comparators is related to the input offset voltage

and the response time given in the specifications.

Figure 8-4 and Figure 8-5 show the output block

diagram for Comparator 1 and 2.

The TRIS bits will still function as an output enable/

disable for the RA2 and RC4 pins while in this mode.

The polarity of the comparator outputs can be changed

using the C1INV and C2INV bits (CMCON0<5:4>).

Timer1 gate source can be configured to use the T1G

pin or Comparator 2 output as selected by the T1GSS

bit (CMCON1<1>). This feature can be used to time the

duration or interval of analog events. The output of

Comparator 2 can also be synchronized with Timer1 by

setting

the

C2SYNC

bit

(CMCON1<0>).

When

enabled, the output of Comparator 2 is latched on the

falling edge of Timer1 clock source. If a prescaler is

used with Timer1, Comparator 2 is latched after the

prescaler. To prevent a race condition, the Comparator

2 output is latched on the falling edge of the Timer1

clock source and Timer1 increments on the rising edge

of its clock source. See the Comparator 2 Block

Diagram (Figure 8-5) and the Timer1 Block Diagram

(Figure 6-1) for more information.

It is recommended to synchronize Comparator 2 with

Timer1 by setting the C2SYNC bit when Comparator 2

is used as the Timer1 gate source. This ensures Timer1

does not miss an increment if Comparator 2 changes

during an increment.

8.5

Comparator Interrupts

The comparator interrupt flags are set whenever there

is a change in the output value of its respective compar-

ator. Software will need to maintain information about

the

status

the

output

bits,

read

from

CMCON0<7:6>, to determine the actual change that

has occurred. The CxIF bits, PIR1<4:3>, are the

Comparator Interrupt Flags. This bit must be reset in

software by clearing it to ‘0’. Since it is also possible to

write a ‘1’ to this register, a simulated interrupt may be

initiated.

The

CxIE

bits

(PIE1<4:3>)

and

the

PEIE

bit

(INTCON<6>) must be set to enable the interrupts. In

addition, the GIE bit must also be set. If any of these

bits are cleared, the interrupt is not enabled, though the

CxIF bits will still be set if an interrupt condition occurs.

The user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

Any read or write of CMCON0. This will end the

mismatch condition.

Clear flag bit CxIF.

A mismatch condition will continue to set flag bit CxIF.

Reading CMCON0 will end the mismatch condition and

allow flag bit CxIF to be cleared.

U-0

R/W-1

R/W-0

—

T1GSS

C2SYNC

bit 7

bit 0

bit 7-2:

Unimplemented: Read as ‘0’

bit 1

T1GSS: Timer1 Gate Source Select bit

Timer1 gate source is T1G pin (RA4 must be configured as digital input)

Timer1 gate source is comparator 2 output

bit 0

C2SYNC: Comparator 2 Synchronize bit

C2 output synchronized with falling edge of Timer1 clock

C2 output not synchronized with Timer1 clock

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

Note:

If a change in the CMCON0 register

(CxOUT) should occur when a read

operation is being executed (start of the Q2

cycle), then the CxIF (PIR1<4:3>) interrupt

flag may not get set.

PIC16F684-E/ST Datasheet(PDF) 61 Page - Microchip Technology

PIC16F684-E/ST Datasheet(HTML) 61 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL