PIC16F684-ESLASHST datasheet(147/164 Pages) MICROCHIP

147 / 164 page

 2004 Microchip Technology Inc.

Preliminary

DS41202C-page 145

PIC16F684

FIGURE 15-9:

PIC16F684 A/D CONVERSION TIMING (NORMAL MODE)

TABLE 15-10: PIC16F684 A/D CONVERSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C

≤ TA ≤ +125°C

Param

No.

Sym

Characteristic

Min

Typ†

Max

Units

Conditions

130

TAD

A/D Clock Period

1.6

—

µsTOSC-based, VREF ≥ 3.0V

3.0*

—

µsTOSC-based, VREF full range

130

TAD

A/D Internal RC

Oscillator Period

3.0*

6.0

9.0*

µs

ADCS<1:0> = 11 (RC mode)

At VDD = 2.5V

2.0*

4.0

6.0*

µsAt VDD = 5.0V

131

TCNV

Conversion Time

(not including

Acquisition Time)(1)

—11

—

TAD

Set GO bit to new data in A/D Result

132

TACQ

Acquisition Time

11.5

—

µs

µs The minimum time is the amplifier

settling time. This may be used if the

“new” input voltage has not changed

by more than 1 LSb (i.e., 4.1 mV @

4.096V) from the last sampled

voltage (as stored on CHOLD).

134

TGO

Q4 to A/D Clock

Start

—TOSC/2

—

If the A/D clock source is selected as

RC, a time of TCY is added before

the A/D clock starts. This allows the

SLEEP

instruction to be executed.

These parameters are characterized but not tested.

† Data in ‘Typ’ column is at 5.0V, 25

°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1:

ADRESH and ADRESL registers may be read on the following TCY cycle.

See Table 9-1 for minimum conditions.

131

130

132

BSF ADCON0, GO

A/D CLK

A/D Data

ADRES

ADIF

Sample

OLD_DATA

Sampling Stopped

DONE

NEW_DATA

Note 1:

If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP

instruction to be executed.

1 TCY

134

(TOSC/2)(1)

1 TCY

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