Z8018010FSC datasheet(53/124 Pages) ZILOG

53 / 124 page

Z 8018x Fam il

M PU Use r M anual

UM005001-ZMP0400

Set bits 6 and 3 to 1 and 0, respectively.

Set the I/O STOP bits (bit 5 of ICR, I/O Address = 3FH) to 1.

Execute the SLEEP instruction.

When the device is in STANDBY mode, it performs similar to the

SYSTEM STOP mode as it exists on the Z80180-class processors, except

that the STANDBY mode stops the external oscillator, internal clocks and

reduces power consumption to 50

µA (typical).

Because the clock oscillator has been stopped, a restart of the oscillator

requires a period of time for stabilization. An 18-bit counter has been

added in the Z8S180Z8L180 to allow for oscillator stabilization. When

the part receives an external IRQ or BUSREQ during STANDBY mode,

the oscillator is restarted and the timer counts down 217 counts before

acknowledgment is sent to the interrupt source.

The recovery source must remain asserted for the duration of the 217

count, otherwise STANDBY restarts.

STANDBY Mode Exit with BUS REQUEST

Optionally, if the BREXT bit (D5 of CPU Control Register) is set to 1, the

Z8S180 exits STANDBY mode when the BUSREQ input is asserted. The

crystal oscillator is then restarted. An internal counter automatically

provides time for the oscillator to stabilize, before the internal clocking

and the system clock output of the Z8S180 are resumed.

The Z8S180 relinquishes the system bus after the clocking is resumed by:

• 3-State the address outputs A19–A0

• 3-State the bus control outputs MREQ, IORQ, RD, and WR

• Asserting BUSACK

The Z8S180 regains the system bus when BUSREQ is deactivated. The

address outputs and the bus control outputs are then driven High. The

STANDBY mode is exited.

Z8018010FSC Datasheet(PDF) 53 Page - Zilog, Inc.