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MPC5675KFF0VMS2R Datasheet(PDF) 78 Page - NXP Semiconductors |
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MPC5675KFF0VMS2R Datasheet(HTML) 78 Page - NXP Semiconductors |
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78 / 147 page  MPC5675K Microcontroller Data Sheet, Rev. 9 Electrical characteristics NXP Semiconductors 78 × 3.12 FMPLL electrical characteristics Table 21. Main oscillator electrical characteristics No. Symbol Parameter Conditions1 1 V DD = 3.0 V to 3.6 V, TJ = –40 to 150 °C, unless otherwise specified. Value Unit Min Typ Max 1FXOSCHS SR Oscillator frequency — 4.0 — 40.0 MHz 2a TXOSCHSSU CC Oscillator start-up time fOSC <16MHz — 6 10 ms 2b fOSC = 16 MHz to 40 MHz — 2 4 3VIH SR Input high level CMOS Schmitt Trigger Oscillator bypass mode 0.65 × VDD —VDD +0.4 V 4VIL SR Input low level CMOS Schmitt Trigger Oscillator bypass mode –0.4 — 0.35 × VDD V Table 22. FMPLL electrical characteristics No. Symbol Parameter Conditions Min Typ Max Unit 1 fREF_CRYSTAL fREF_EXT D FMPLL reference frequency range1, 2 Crystal reference 4 — 120 MHz 2fPLL_IN D Phase detector input frequency range (after pre-divider) —4 — 16 MHz 3fFMPLLOUT D Clock frequency range in normal mode See the FMPLL chapter in the chip reference manual for more details on PLL configuration. 16 — 256 MHz 4fFREE P Free running frequency Measured using clock division (typically ÷16) 19 — 60 MHz 5fsys D On-chip FMPLL frequency2 — — — 180 MHz 6tCYC D System clock period — — — 1 / fsys ns 7a fLORL fLORH D Loss of reference frequency window3 Lower limit 1.6 — 3.7 MHz 7b Upper limit 24 — 56 8fSCM D Self-clocked mode frequency4,5 — 20 — 150 MHz 9tLOCK PLock time Stable oscillator (fPLLIN =4MHz), stable VDD — — 200 µs 10 tlpll D FMPLL lock time 6, 7 — — — 200 μs 11 tdc D Duty cycle of reference —20 — 80 % 12a CJITTER T CLKOUT period jitter8,9,10,11 Peak-to-peak (clock edge to clock edge), fFMPLLOUT maximum12 — — 160 ps 12b Long-term jitter (avg. over 2 ms interval), fFMPLLOUT maximum —— 6 ns 13 Δt PKJIT T Single period jitter (peak to peak) PHI @ 16 MHz, Input clock @ 4 MHz —— ±500 ps |
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