SH79F1616PSLASH032PR datasheet(67/102 Pages) SINOWEALTH

67 / 102 page

SH79F1616

Any instruction that uses SBUF as a destination register (“write to SBUF” signal) will start the transmission. The next system

clock tells the Tx control block to commence a transmission. The data shift occurs at the falling edge of the SHIFT CLOCK, and

the contents of the transmit shift register is shifted one position to the right. As data bits shift to the right, zeros come in from the

left. After transmission of all 8 bits in the transmit shift register, the Tx control block will deactivates SEND and sets TI (SCON.1)

at the rising edge of the next system clock.

Write to SBUF

RxD

Send Timing of Mode 0

TxD

Reception is initiated by the condition REN (SCON.4) = 1 and RI (SCON.0) = 0. The next system clock activates RECEIVE. The

data latch occurs at the rising edge of the SHIFT CLOCK, and the contents of the receive shift register are shifted one position

to the left. After the receiving of all 8 bits into the receive shift register, the RX control block will deactivates RECEIVE and sets

RI at the rising edge of the next system clock, and the reception will not be enabled till the RI is cleared by software.

RxD

Receive Timing of Mode 0

TxD

Mode1: 8-Bit EUART, Variable Baud Rate, Asynchronous Full-Duplex

This mode provides the 10 bits full duplex asynchronous communication. The 10 bits consist of a start bit (logical 0), 8 data bits

(LSB first), and a stop bit (logical 1). When receiving, the eight data bits are stored in SBUF and the stop bit goes into RB8

(SCON.2). The serial receive and transmit baud rate is 1/16 of the Timer4/2 overflow (Refer to Baud Rate Section for details).

The functional block diagram is shown below.

Timer 4 Overflow

SERIAL

CONTROLLER

TX CLOCK

TX START

TX SHIFT

RX CLOCK

LOAD SBUF

RX START

RX SHIFT

Serial Port Interrupt

CLOCK

SIN

PAROUT

RXD

Read SBUF

Internal

Data Bus

Receive Shift Register

Timer 2 Overflow

1-TO-0

DETECTOR

Write to SBUF

BIT

DETECTOR

SBUF

RB8

SAMPLE

TXD

PARIN

LOAD

CLOCK

SOUT

Internal

Data Bus

Transmit Shift Register

START

TB8

STOP

TCLK

RCLK

SH79F1616P/032PR Datasheet(PDF) 67 Page - SINOWEALTH Electronic Ltd

SH79F1616P/032PR Datasheet(HTML) 67 Page - SINOWEALTH Electronic Ltd

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