UPSD3422_V01 datasheet(207/300 Pages) STMICROELECTRONICS

207 / 300 page

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28.5

PSD module detailed operation

Specific details are given here for the following key functional areas on the PSD module:

●

Flash Memories

●

PLDs (DPLD and GPLD)

●

I/O Ports

●

Power Management

●

JTAG ISP and Debug Interface

28.5.1

Flash memory operation

The Flash memories are accessed through the 8032 Address, Data, and Control Bus

interfaces. Flash memories (and SRAM) cannot be accessed by any other bus master other

than the 8032 MCU (these are not dual-port memories).

The 8032 cannot write to Flash memory as it would an SRAM (supply address, supply data,

supply WR strobe, assume the data was correctly written to memory). Flash memory must

first be “unlocked” with a special instruction sequence of byte WRITE operations to invoke

an internal algorithm inside either Flash memory array, then a single data byte is written

(programmed) to the Flash memory array, then programming status is checked by a byte

READ operation or by checking the Ready/Busy pin (PC3). Table 163 on page 209 lists all

of the special instruction sequences to program a byte to either of the Flash memory arrays,

erase the arrays, and check for different types of status from the arrays.

PMMR0

B0h

Power management register 0.

WRITE and READ.

Table 200

page 249

PMMR2

B4h

Power management register 2.

WRITE and READ.

Table 201

page 249

PMMR3

C7h

Power management register 3.

WRITE and READ. However,

Bit 1 can be cleared only by a

reset condition.

Table 202

page 250

Page

E0h

Memory page register. WRITE

and READ.

Table 62

page 194

VM (Virtual

Memory)

E2h

Places PSD module memories

into 8032 Program Address

Space and/or 8032 XDATA

Address Space. (VM overrides

initial non-volatile setting that

was specified in PSDsoft

Express. Reset restores initial

setting)

Table 160

page 203

Table 162.

CSIOP registers and their offsets (in hexadecimal) (continued)

name

Port A

(80-pin)

Port B Port C Port D Other

Description

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