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STM32U5A5QJ Datasheet(PDF) 47 Page - STMicroelectronics

Part # STM32U5A5QJ
Description  Ultra-low-power Arm® Cortex®-M33 32-bit MCUTrustZone®FPU,240 DMIPS, 4 MB Flash, 2.5 MB SRAM, LTDC, MIPI® DSI, crypto
PDF  382 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32U5A5QJ Datasheet(HTML) 47 Page - STMicroelectronics

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DS13543 Rev 1
47/382
STM32U5Axxx
Functional overview
99
WWDG (window
watchdog)
OO
-
--
--
--
--
--
SysTick timer
O
O
-
--
--
--
--
--
MDF1 (multi-function
digital filter)
OO
O(17)
O(17)
-
--
--
--
--
ADF1 (audio digital
filter)
OO
O(17)
O(17)
O(17)
O(17)
-
--
--
--
LTDC
O
O
-
--
--
--
--
--
DSI
O
O
-
--
--
--
--
--
GFXMMU
O
O
-
--
--
--
--
--
GPU2D
O
O
-
--
--
--
--
--
DCMI (digital camera
interface)
OO
-
--
--
--
--
--
PSSI (parallel
synchronous slave
interface)
OO
CORDIC
coprocessor
OO
-
--
--
--
--
--
FMAC (filter
mathematical
accelerator)
OO
-
--
--
--
--
--
TSC (touch sensing
controller)
OO
-
--
--
--
--
--
RNG (true random
number generator)
OO
-
--
--
--
--
--
AES and secure AES
O
O
-
--
--
--
--
--
PKA (public key
accelerator)
OO
-
--
--
--
--
--
OTFDEC (on-the-fly
decryption)
OO
-
--
--
--
--
--
HASH accelerator
O
O
-
--
--
--
--
--
CRC calculation unit
O
O
-
--
--
--
--
--
GPIOs
O
O
O
OO
O
-
(18)
24
pins
-
(18)
24
pins
-
(19)
24
pins
-
1. Y = yes (enabled). O = optional (disabled by default, can be enabled by software). - = not available.
Gray cells highlight the wake-up capability in each mode.
2. The flash memory can be configured in power-down mode. By default, it is not in power-down mode.
3. The SRAMs can be powered on or off independently.
4. The SRAM clock can be gated on or off independently.
5. ECC error interrupt or NMI wake-up from Stop mode.
Table 10. Functionalities depending on the working mode(1) (continued)
Peripheral
Run
Sleep
Stop 0/1
Stop 2
Stop 3
Standby Shutdown
VBAT
-
-
-
-
-



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