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STM32U5A5QJ Datasheet(PDF) 93 Page - STMicroelectronics |
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STM32U5A5QJ Datasheet(HTML) 93 Page - STMicroelectronics |
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93 / 382 page  DS13543 Rev 1 93/382 STM32U5Axxx Functional overview 99 3.51 Serial peripheral interfaces (SPI) The devices embed three serial peripheral interfaces (SPI) that can be used to communicate with external devices while using the specific synchronous protocol. The SPI protocol supports half-duplex, full-duplex and simplex synchronous, serial communication with external devices. The interface can be configured as master or slave and can operate in multi-slave or multi-master configurations. The device configured as master provides communication clock (SCK) to the slave device. The slave select (SS) and ready (RDY) signals can be applied optionally just to setup communication with concrete slave and to assure it handles the data flow properly. The Motorola® data format is used by default, but some other specific modes are supported as well. The SPI main features are: • Full-duplex synchronous transfers on three lines • Half-duplex synchronous transfer on two lines (with bidirectional data line) • Simplex synchronous transfers on two lines (with unidirectional data line) • 4-bit to 32-bit data size selection or fixed to 8-bit and 16-bit only • Multi master or multi slave mode capability • Dual-clock domain, separated clock for the peripheral kernel that can be independent of PCLK • Baud rate prescaler up to kernel frequency/2 or bypass from RCC in Master mode • Protection of configuration and setting • Hardware or software management of SS for both master and slave • Adjustable minimum delays between data and between SS and data flow • Configurable SS signal polarity and timing, MISO x MOSI swap capability • Programmable clock polarity and phase • Programmable data order with MSB-first or LSB-first shifting • Programmable number of data within a transaction to control SS and CRC • Dedicated transmission and reception flags with interrupt capability • SPI Motorola® and Texas Instruments® formats support • Hardware CRC feature can secure communication at the end of transaction by: – Adding CRC value in Tx mode – Automatic CRC error checking for Rx mode • Error detection with interrupt capability in case of data overrun, CRC error, data underrun at slave, mode fault at master • Two 16x or 8x 8-bit embedded Rx and TxFIFOs with DMA capability • Programmable number of data in transaction • Configurable FIFO thresholds (data packing) • Configurable behavior at slave underrun condition (support of cascaded circular buffers) • Autonomous functionality in Stop modes (handling of the transaction flow and required clock distribution) with wake-up from stop capability • Optional status pin RDY signalizing the slave device ready to handle the data flow. |
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