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STM32U5A5QJ Datasheet(PDF) 96 Page - STMicroelectronics

Part # STM32U5A5QJ
Description  Ultra-low-power Arm® Cortex®-M33 32-bit MCUTrustZone®FPU,240 DMIPS, 4 MB Flash, 2.5 MB SRAM, LTDC, MIPI® DSI, crypto
PDF  382 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32U5A5QJ Datasheet(HTML) 96 Page - STMicroelectronics

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Functional overview
STM32U5Axxx
96/382
DS13543 Rev 1
•
Data transfer up to 208 Mbyte/s for the 8-bit mode
(Depending maximum allowed I/O speed).
•
Data and command output enable signals to control external bidirectional drivers
•
IDMA linked list support
The MultiMediaCard/SD bus connects cards to the host.
The current version of the SDMMC supports only one SD/SDIO/e•MMC card at any one
time and a stack of e•MMC.
When SDMMC peripherals are used simultaneously:
•
Only one can be used in e•MMC with 8-bit bus width.
•
The SDMMC1 SDIO voltage switch use is mutually exclusive with SDMMC2 interfacing
e•MMC with 8-bit bus width, as follows:
–
If SDMMC1 has to support SDIO UHS-I modes (SDR12, SDR25, SDR50,
SDR104 or DDR50), SDMMC2 cannot support e•MMC with 8-bit bus width.
–
if SDMMC2 has to support e•MMC with 8-bit bus width, SDMMC1 supports only
SDIO default mode and high-speed mode.
3.54
Controller area network (FDCAN)
The controller area network (CAN) subsystem consists of one CAN module, a shared
message RAM memory and a configuration block.
The modules (FDCAN) are compliant with ISO 11898-1: 2015 (CAN protocol specification
version 2.0 part A, B) and CAN FD protocol specification version 1.0.
A 0.8-Kbyte message RAM implements filters, receives FIFOs, transmits event FIFOs and
transmits FIFOs.
The FDCAN main features are:
•
Conform with CAN protocol version 2.0 part A, B and ISO 11898-1: 2015, -4
•
CAN FD with maximum 64 data bytes supported
•
CAN error logging
•
AUTOSAR and J1939 support
•
Improved acceptance filtering
•
2 receive FIFOs of three payloads each (up to 64 bytes per payload)
•
Separate signaling on reception of high priority messages
•
Configurable transmit FIFO / queue of three payload (up to 64 bytes per payload)
Table 25. SDMMC features
SDMMC modes/features(1)
1. X = supported.
SDMMC1
SDMMC2
Variable delay (SDR104, HS200)
X
X
SDMMC_CKIN
X
-
SDMMC_CDIR, SDMMC_D0DIR
X
-
SDMMC_D123DIR
X
-



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