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STM32U5A5QJ Datasheet(PDF) 61 Page - STMicroelectronics |
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STM32U5A5QJ Datasheet(HTML) 61 Page - STMicroelectronics |
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61 / 382 page ![]() DS13543 Rev 1 61/382 STM32U5Axxx Functional overview 99 The CORDIC main features are: • 24-bit CORDIC rotation engine • Circular and hyperbolic modes • Rotation and vectoring modes • Functions: sine, cosine, sinh, cosh, atan, atan2, atanh, modulus, square root, natural logarithm • Programmable precision • Low-latency AHB slave interface • Results can be read as soon as ready without polling or interrupt • DMA read and write channels • Multiple register read/write by DMA 3.25 Filter math accelerator (FMAC) The FMAC performs arithmetic operations on vectors. It comprises a MAC (multiplier/accumulator) unit, together with address generation logic that allows it to index vector elements held in local memory. The unit includes support for circular buffers on input and output, that allows digital filters to be implemented. Both finite and infinite impulse response filters can be done. The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing up the processor for other tasks. In many cases it can accelerate such calculations compared to a software implementation, resulting in a speed-up of time critical tasks. The FMAC main features are: • 16 x 16-bit multiplier • 24 + 2-bit accumulator with addition and subtraction • 16-bit input and output data • 256 x 16-bit local memory • Up to three areas can be defined in memory for data buffers (two input, one output), defined by programmable base address pointers and associated size registers • Input and output buffers can be circular • Filter functions: FIR, IIR (direct form 1) • Vector functions: dot product, convolution, correlation • AHB slave interface • DMA read and write data channels 3.26 Flexible static memory controller (FSMC) The FSMC includes two memory controllers: • NOR/PSRAM memory controller • NAND/memory controller The FSMC is also named flexible memory controller (FMC). |
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