STM32U5A5QJ datasheet(17/382 Pages) STMICROELECTRONICS

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DS13543 Rev 1

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STM32U5Axxx

Description

The STM32U5Axxx devices belong to an ultra-low-power microcontrollers family

(STM32U5 Series) based on the high-performance Arm® Cortex®-M33 32-bit RISC core.

They operate at a frequency of up to 160 MHz.

The Cortex®-M33 core features a single-precision FPU (floating-point unit), that supports all

the Arm® single-precision data-processing instructions and all the data types.

The Cortex®-M33 core also implements a full set of DSP (digital signal processing)

instructions and a MPU (memory protection unit) that enhances the application security.

The devices embed high-speed memories (4 Mbytes of flash memory and 2.5 Mbytes of

SRAM), a FSMC (flexible external memory controller) for static memories (for devices with

packages of 100 pins and more), two Octo-SPI and one Hexadeca-SPI memory interfaces

(at least one Quad-SPI available on all packages) and an extensive range of enhanced I/Os

and peripherals connected to three APB buses, three AHB buses and a 32-bit multi-AHB

bus matrix.

The devices offer security foundation compliant with the TBSA (trusted-based security

architecture) requirements from Arm®. It embeds the necessary security features to

implement a secure boot, secure data storage and secure firmware update. Besides these

capabilities, the devices incorporate a secure firmware installation feature, that allows the

customer to secure the provisioning of the code during its production. A flexible life cycle is

managed thanks to multiple levels of readout protection and debug unlock with password.

Firmware hardware isolation is supported thanks to securable peripherals, memories and

I/Os, and privilege configuration of peripherals and memories.

The devices feature several protection mechanisms for embedded flash memory and

SRAM: readout protection, write protection, secure and hide protection areas.

The devices embed several peripherals reinforcing security: a fast AES coprocessor,

a secure AES coprocessor with DPA resistance and hardware unique key that can be

shared by hardware with fast AES, a PKA (public key accelerator) with DPA resistance,

an on-the-fly decryption engine for Octo-SPI external memories, a HASH hardware

accelerator, and a true random number generator.

The devices offer active tamper detection and protection against transient and

environmental perturbation attacks, thanks to several internal monitoring generating secret

data erase in case of attack. This helps to fit the PCI requirements for point of sales

applications.

The devices offer two fast 14-bit ADCs (2.5 Msps), one 12-bit ADC (2.5 Msps), two

comparators, two operational amplifiers, two DAC channels, an internal voltage reference

buffer, a low-power RTC, four 32-bit general-purpose timers, two 16-bit PWM timers

dedicated to motor control, three 16-bit general-purpose timers, two 16-bit basic timers and

four 16-bit low-power timers.

The devices offer a rich set of graphic features: Neo-Chrom GPU (GPU2D) for fast texture

mapping, scaling and rotation, Chrom-ART (DMA2D) for smooth motion and transparency

effects, Chrom-GRC (GFXMMU) for memory optimization, MIPI® DSI Host controller with

two DSI lanes running at up to 500 Mbit/s each, and LCD-TFT controller (LTDC).

The devices support a MDF (multi-function digital filter) with six filters dedicated to the

connection of external sigma-delta modulators. Another low-power digital filter dedicated to

audio signals is embedded (ADF), with one filter supporting sound-activity detection.

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