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STM32U5A5QJ Datasheet(PDF) 66 Page - STMicroelectronics |
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STM32U5A5QJ Datasheet(HTML) 66 Page - STMicroelectronics |
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66 / 382 page ![]() Functional overview STM32U5Axxx 66/382 DS13543 Rev 1 The ADC1/2 main features are: • High-performance features – Dual mode operation – 14-, 12-, 10- or 8-bit configurable resolution – A/D conversion time independent from the AHB bus clock frequency – Faster conversion time by lowering resolution – Management of single-ended or differential inputs (programmable per channels) – Fast data handling thanks to the AHB slave bus interface – Self-calibration (both offset and linearity) – Channel-wise programmable sampling time – Flexible sampling time control – Up to four injected channels (analog inputs assignment to regular or injected channels is fully configurable) – Fast context switching thanks to the hardware assistant that prepares the context of the injected channels – Data alignment with in-built data coherency – Data can be managed by GPDMA for regular channel conversions with FIFO – Data can be routed to MDF for post processing – Four dedicated data registers for the injected channels • Oversampler – 32-bit data register – Oversampling ratio adjustable from 2 to 1024 – Programmable data right and left shift • Data preconditioning – Gain compensation – Offset compensation • Low-power features – Speed adaptive low-power mode to reduce ADC consumption when operating at low frequency – Slow bus frequency application while keeping optimum ADC performance – Automatic control to avoid ADC overrun in low AHB bus clock frequency application (auto-delayed mode) • ADC features an external analog input channel: – Up to 17 channels from dedicated GPIO pads • Three additional internal dedicated channels: – One channel for internal reference voltage (VREFINT) – One channel for internal temperature sensor (VSENSE) – One channel for VBAT monitoring channel (VBAT/4) • Start-of-conversion can be initiated: – by software for both regular and injected conversions – by hardware triggers with configurable polarity (internal timers events or GPIO input events) for both regular and injected conversions |
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