PIC18F6410ESLASHPTSQTP datasheet(161/404 Pages) MICROCHIP

161 / 404 page

 2004 Microchip Technology Inc.

Preliminary

DS39635A-page 159

PIC18F6310/6410/8310/8410

15.0

CAPTURE/COMPARE/PWM

(CCP) MODULES

PIC18F6310/6410/8310/8410 devices have three CCP

(Capture/Compare/PWM) modules, labelled CCP1,

CCP2 and CCP3. All modules implement standard

Capture, Compare and Pulse-Width Modulation (PWM)

modes.

Each CCP module contains a 16-bit register which can

operate as a 16-bit Capture register, a 16-bit Compare

For the sake of clarity, all CCP module operation in the

following sections is described with respect to CCP2,

but are equally applicable to CCP1 and CCP3.

CCPXCON: CCP1/CCP2/CCP3 CONTROL REGISTER

U-0

R/W-0

—

DCxB1

DCxB0

CCPxM3

CCPxM2

CCPxM1 CCPxM0

bit 7

bit 0

bit 7-6

Unimplemented: Read as ‘0’

bit 5-4

DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCP Module x

Capture mode:

Unused.

Compare mode:

Unused.

PWM mode:

These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM Duty Cycle

CCPRxL.

bit 3-0

CCPxM3:CCPxM0: CCP Module x Mode Select bits

0000

= Capture/Compare/PWM disabled (resets CCPx module)

0001

= Reserved

0010

= Compare mode, toggle output on match (CCPxIF bit is set)

0011

= Reserved

0100

= Capture mode, every falling edge

0101

= Capture mode, every rising edge

0110

= Capture mode, every 4th rising edge

0111

= Capture mode, every 16th rising edge

1000

= Compare mode: initialize CCP pin low; on compare match, force CCP pin high

(CCPIF bit is set)

1001

= Compare mode: initialize CCP pin high; on compare match, force CCP pin low

(CCPIF bit is set)

1010

= Compare mode: generate software interrupt on compare match (CCPIF bit is set,

CCP pin reflects I/O state)

1011

= Compare mode: trigger special event, reset timer, start A/D conversion on

CCP2 match (CCPIF bit is set)(1,2)

11xx

=PWM mode

Note 1: The special event trigger on CCP1 will reset the timer but not start an A/D

conversion on a CCP1 match.

2: For CCP3, the special event trigger is not available. This mode functions the same

as Compare Generate Interrupt mode (CCP3M3:CCP3M0 = 1010).

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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