PIC18F6410ESLASHPTSQTP datasheet(164/404 Pages) MICROCHIP

164 / 404 page

PIC18F6310/6410/8310/8410

DS39635A-page 162

Preliminary

 2004 Microchip Technology Inc.

15.2.3

SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep bit

CCP2IE (PIE2<1>) clear to avoid false interrupts and

should clear the flag bit, CCP2IF, following any such

change in operating mode.

15.2.4

CCP PRESCALER

There are four prescaler settings in Capture mode; they

are specified as part of the operating mode selected by

the mode select bits (CCP2M3:CCP2M0). Whenever

the CCP module is turned off, or the CCP module is not

in Capture mode, the prescaler counter is cleared. This

means that any Reset will clear the prescaler counter.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleared, therefore, the first capture may be from

non-zero

prescaler.

Example 15-1

shows

the

recommended method for switching between capture

prescalers. This example also clears the prescaler

counter and will not generate the “false” interrupt.

EXAMPLE 15-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

15.3

Compare Mode

In Compare mode, the 16-bit CCPR2 register value is

constantly compared against either the TMR1 or TMR3

pin can be:

• driven high

• driven low

• toggled (high-to-low or low-to-high)

• remain unchanged (that is, reflects the state of the

I/O latch)

The action on the pin is based on the value of the mode

select bits (CCP2M3:CCP2M0). At the same time, the

interrupt flag bit, CCP2IF, is set.

15.3.1

CCP PIN CONFIGURATION

The user must configure the CCPx pin as an output by

clearing the appropriate TRIS bit.

15.3.2

TIMER1/TIMER3 MODE SELECTION

Timer1 and/or Timer3 must be running in Timer mode,

or Synchronized Counter mode, if the CCP module is

using the compare feature. In Asynchronous Counter

mode, the compare operation may not work.

15.3.3

SOFTWARE INTERRUPT MODE

When the Generate Software Interrupt mode is chosen

(CCP2M3:CCP2M0 = 1010), the CCP2 pin is not

affected. Only a CCP interrupt is generated if enabled

and the CCP2IE bit is set.

15.3.4

SPECIAL EVENT TRIGGERS

CCP1 and CCP2 are both equipped with a special

event trigger. This is an internal hardware signal,

generated in Compare mode, to trigger actions by other

modules. The special event trigger is enabled by

selecting the Compare Special Event Trigger mode

(CCP2M3:CCP2M0 = 1011).

For either CCP module, the special event trigger resets

the timer register pair for whichever timer resource is

currently assigned as the module’s time base. This

allows the CCPRx registers to serve as a programmable

period register for either timer.

The special event trigger for CCP2 can also start an

A/D conversion. In order to do this, the A/D converter

must already be enabled.

CCP3 is not equipped with a special event trigger.

Selecting the Compare Special Event Trigger mode for

this device (CCP3M3:CCP3M0 = 1011) is functionally

the same as selecting the Generate Software Interrupt

mode (CCP3M3:CCP3M0 = 1010).

CLRF

CCP2CON

; Turn CCP module off

MOVLW

NEW_CAPT_PS

; Load WREG with the

; new prescaler mode

; value and CCP ON

MOVWF

CCP2CON

; Load CCP2CON with

; this value

Note:

Clearing the CCP2CON register will force

the RC1 or RE7 compare output latch

(depending on device configuration) to the

default low level. This is not the PORTC or

PORTE I/O data latch.

Note:

The special event trigger of CCP1 only

resets Timer1/Timer3 and cannot start an

A/D conversion even when the A/D

converter is enabled.

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