S75WS256NDFBAWMB datasheet(109/216 Pages) SPANSION

109 / 216 page

February 17, 2005 S75WS-N-00_00_A0

S75WS256Nxx Based MCPs

107

Data

Sheet

Refer to the Synchronous/Burst Read section for RESET# parameters and to Figure 25.9 for the

timing diagram.

18.12 Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the

high impedance state.

18.13 Hardware Data Protection

The following hardware data protection measures prevent accidental erasure or programming,

which might otherwise be caused by spurious system level signals during VCC power-up and

power-down transitions, or from system noise.

18.13.1 Low VCC Write Inhibit

When VCC is less than VLKO, the device does not accept any write cycles. This protects data during

VCC power-up and power-down. The command register and all internal program/erase circuits are

disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is

greater than VLKO. The system must provide the proper signals to the control inputs to prevent

unintentional writes when VCC is greater than VLKO.

18.13.2 Write Pulse Glitch Protection

Noise pulses do not initiate a write cycle.

18.13.3 Logical Inhibit

Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate

a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.

S75WS256NDFBAWMB Datasheet(PDF) 109 Page - SPANSION