S75WS256NDFBAWMB datasheet(132/216 Pages) SPANSION

132 / 216 page

130

S75WS256Nxx Based MCPs

S75WS-N-00_00_A0 February 17, 2005

Data

Sheet

Notes:

1. Figure shows total number of wait states set to ten cycles. The total number of wait states can be programmed from

three cycles to thirteen cycles.

2. If any burst address occurs at address + 1, address + 2, ..., or address + 7, additional clock delay cycles are inserted,

and are indicated by RDY.

3. The device is in synchronous mode.

4. In order for the device to operate at 80Mhz/66Mhz/54Mhz, there is an additional wait state latency of 2/1/0 accordingly,

every 4 clock cycles with the first data being read.

Figure 25.3 CLK Synchronous Burst Mode Read

Da + 1

Da + n

OE#

Data (n)

Addresses

AVD#

RDY (n)

CLK

CE#

tCES

tACS

tAVC

tAVD

tACH

tOE

tRACC

tOEZ

tCEZ

tIACC

tBDH

10 cycles for initial access shown.

18.5 ns typ. (54 MHz)

Hi-Z

tRDYS

tBACC

Da + 2

Da + 1

Da + n

Data (n + 1)

RDY (n + 1)

Hi-Z

Da + 2

Da + 1

Da + n

Data (n + 2)

RDY (n + 2)

Hi-Z

Da + 1

Da + n

Data (n + 3)

RDY (n + 3)

Hi-Z

tCR

S75WS256NDFBAWMB Datasheet(PDF) 132 Page - SPANSION

S75WS256NDFBAWMB Datasheet(HTML) 132 Page - SPANSION

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL