MC908QT4MPE datasheet(47/184 Pages) FREESCALE

47 / 184 page

Input/Output Registers

MC68HC908QY/QT Family Data Sheet, Rev. 5

Freescale Semiconductor

3.7.2 ADC Data Register

One 8-bit result register is provided. This register is updated each time an ADC conversion completes.

3.7.3 ADC Input Clock Register

This register selects the clock frequency for the ADC.

ADIV2–ADIV0 — ADC Clock Prescaler Bits

ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate

the internal ADC clock. Table 3-2 shows the available clock configurations. The ADC clock frequency

should be set between fADIC(MIN) and fADIC(MAX). The analog input level should remain stable for the

entire conversion time (maximum = 17 ADC clock cycles).

Address: $003E

Bit 7

654321

Bit 0

Read:

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

Write:

Reset:

Indeterminate after reset

= Unimplemented

Figure 3-4. ADC Data Register (ADR)

Address: $003F

Bit 7

654321

Bit 0

Read:

ADIV2

ADIV1

ADIV0

00000

Write:

Reset:

00000000

= Unimplemented

Figure 3-5. ADC Input Clock Register (ADICLK)

Table 3-2. ADC Clock Divide Ratio

ADIV2

ADIV1

ADIV0

ADC Clock Rate

Bus clock ÷ 1

Bus clock ÷ 2

Bus clock ÷ 4

Bus clock ÷ 8

Bus clock ÷ 16

X = don’t care

MC908QT4MPE Datasheet(PDF) 47 Page - Freescale Semiconductor, Inc

MC908QT4MPE Datasheet(HTML) 47 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL