MC908QT4MPE datasheet(59/184 Pages) FREESCALE

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COP Control Register

MC68HC908QY/QT Family Data Sheet, Rev. 5

Freescale Semiconductor

6.3.7 COPRS (COP Rate Select)

The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1

(CONFIG1). See Chapter 5 Configuration Register (CONFIG).

6.4 COP Control Register

The COP control register (COPCTL) is located at address $FFFF and overlaps the reset vector. Writing

any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF

returns the low byte of the reset vector.

6.5 Interrupts

The COP does not generate CPU interrupt requests.

6.6 Monitor Mode

The COP is disabled in monitor mode when VTST is present on the IRQ pin.

6.7 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-consumption standby modes.

6.7.1 Wait Mode

The COP continues to operate during wait mode. To prevent a COP reset during wait mode, periodically

clear the COP counter.

6.7.2 Stop Mode

Stop mode turns off the BUSCLKX4 input to the COP and clears the SIM counter. Service the COP

immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering

or exiting stop mode.

6.8 COP Module During Break Mode

The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary

Address: $FFFF

Bit 7

654321

Bit 0

Read:

LOW BYTE OF RESET VECTOR

Write:

CLEAR COP COUNTER

Reset:

Unaffected by reset

Figure 6-2. COP Control Register (COPCTL)

MC908QT4MPE Datasheet(PDF) 59 Page - Freescale Semiconductor, Inc