MC908QT4MPE datasheet(77/184 Pages) FREESCALE

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Registers

MC68HC908QY/QT Family Data Sheet, Rev. 5

Freescale Semiconductor

8.7.1 IRQ Input Pins (IRQ)

The IRQ pin provides a maskable external interrupt source. The IRQ pin contains an internal pullup

device.

8.8 Registers

The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. See

Chapter 5 Configuration Register (CONFIG).

The INTSCR has the following functions:

•

Shows the state of the IRQ flag

•

Clears the IRQ latch

•

Masks the IRQ interrupt request

•

Controls triggering sensitivity of the IRQ interrupt pin

IRQF — IRQ Flag

This read-only status bit is set when the IRQ interrupt is pending.

1 = IRQ interrupt pending

0 = IRQ interrupt not pending

ACK — IRQ Interrupt Request Acknowledge Bit

Writing a 1 to this write-only bit clears the IRQ latch. ACK always reads as 0.

IMASK — IRQ Interrupt Mask Bit

Writing a 1 to this read/write bit disables the IRQ interrupt request.

1 = IRQ interrupt request disabled

0 = IRQ interrupt request enabled

MODE — IRQ Edge/Level Select Bit

This read/write bit controls the triggering sensitivity of the IRQ pin.

1 = IRQ interrupt request on falling edges and low levels

0 = IRQ interrupt request on falling edges only

Address: $001D

Bit 7

654321

Bit 0

Read:

0000

IRQF

IMASK

MODE

Write:

ACK

Reset:

00000000

= Unimplemented

Figure 8-3. IRQ Status and Control Register (INTSCR)

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