MC908QT4MPE datasheet(87/184 Pages) FREESCALE

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LVI Status Register

MC68HC908QY/QT Family Data Sheet, Rev. 5

Freescale Semiconductor

10.4 LVI Status Register

The LVI status register (LVISR) indicates if the VDD voltage was detected below the VTRIPF level while

LVI resets have been disabled.

LVIOUT — LVI Output Bit

This read-only flag becomes set when the VDD voltage falls below the VTRIPF trip voltage and is cleared

when VDD voltage rises above VTRIPR. The difference in these threshold levels results in a hysteresis

that prevents oscillation into and out of reset (see Table 10-1). Reset clears the LVIOUT bit.

10.5 LVI Interrupts

The LVI module does not generate interrupt requests.

10.6 Low-Power Modes

The STOP and WAIT instructions put the MCU in low power-consumption standby modes.

10.6.1 Wait Mode

If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can

generate a reset and bring the MCU out of wait mode.

10.6.2 Stop Mode

When the LVIPWRD bit in the configuration register is cleared and the LVISTOP bit in the configuration

can generate a reset and bring the MCU out of stop mode.

Address: $FE0C

Bit 7

543

Bit 0

Read:

LVIOUT

000

Write:

Reset:

000

= Unimplemented

= Reserved

Figure 10-2. LVI Status Register (LVISR)

Table 10-1. LVIOUT Bit Indication

VDD

LVIOUT

VDD > VTRIPR

VDD < VTRIPF

VTRIPF < VDD < VTRIPR

Previous value

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