MC908QT4MPE datasheet(55/184 Pages) FREESCALE

55 / 184 page

Functional Description

MC68HC908QY/QT Family Data Sheet, Rev. 5

Freescale Semiconductor

LVIPWRD — LVI Power Disable Bit

LVIPWRD disables the LVI module.

1 = LVI module power disabled

0 = LVI module power enabled

LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit

LVI5OR3 selects the voltage operating mode of the LVI module. The voltage mode selected for the

LVI should match the operating VDD for the LVI’s voltage trip points for each of the modes.

1 = LVI operates in 5-V mode

0 = LVI operates in 3-V mode

NOTE

The LVI5OR3 bit is cleared by a power-on reset (POR) only. Other resets

will leave this bit unaffected.

SSREC — Short Stop Recovery Bit

SSREC enables the CPU to exit stop mode with a delay of 32 BUSCLKX4 cycles instead of a 4096

BUSCLKX4 cycle delay.

1 = Stop mode recovery after 32 BUSCLKX4 cycles

0 = Stop mode recovery after 4096 BUSCLKX4 cycles

NOTE

Exiting stop mode by an LVI reset will result in the long stop recovery.

The system stabilization time for power-on reset and long stop recovery (both 4096 BUSCLKX4

cycles) gives a delay longer than the LVI enable time for these startup scenarios. There is no period

where the MCU is not protected from a low-power condition. However, when using the short stop

recovery configuration option, the 32 BUSCLKX4 delay must be greater than the LVI’s turn on time to

avoid a period in startup where the LVI is not protecting the MCU.

STOP — STOP Instruction Enable Bit

STOP enables the STOP instruction.

1 = STOP instruction enabled

0 = STOP instruction treated as illegal opcode

COPD — COP Disable Bit

COPD disables the COP module.

1 = COP module disabled

0 = COP module enabled

MC908QT4MPE Datasheet(PDF) 55 Page - Freescale Semiconductor, Inc