STE10A datasheet(59/82 Pages) STMICROELECTRONICS

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STE10/100A

Registers and descriptors description

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Table 10.

Transceiver registers description

Bit #

Name

Description

Default

RW type

XR0(offset = b4h) - XCR, XCVR control register. The default value is chosen as listed below.

XRST

Transceiver reset control.

1: reset transceiver. This bit will be cleared by

STE10/100A after transceiver reset has

completed.

0R/W

XLBEN

Transceiver loop-back mode select.

1: transceiver loop-back mode is selected. OM

(CSR6 bits 11,10) of must contain 00.

0R/W

SPSEL

Network speed select. This bit will be ignored if

Auto-negotiation is enabled (ANEN, XR0 bit 12).

1:100Mbps is selected.

0:10Mbps is selected.

1R/W

ANEN

Auto-negotiation ability control.

1: Auto-negotiation function is enabled.

0: Auto-negotiation is disabled.

1R/W

PDEN

Power down mode control.

1: transceiver power-down mode is selected. In

this mode, the STE10/100A transceivers are

turned off.

0R/W

---

reserved

RSAN

Re-start auto-negotiation process control.

1: Auto-negotiation process will be restarted.

This bit will be cleared by STE10/100A after the

Auto-negotiation has restarted.

0R/W

DPSEL

Full/half duplex mode select.

1: full duplex mode is selected. This bit will be

ignored if auto-negotiation is enabled (ANEN,

XR0 bit 12).

0R/W

7COLEN

Collision test control.

1: collision test is enabled.

0R/W

6~0

---

Reserved

R/W = Read/Write able. RO = Read only.

XR1(offset = b8h) - XSR, XCVR status register. All the bits of this register are read only.

100BASE-T4 ability.

Always 0, since STE10/100A has no T4 ability.

0RO

TXFD

100BASE-TX full duplex ability.

Always 1, since STE10/100A has 100BASE-TX

full duplex ability.

1RO

TXHD

100BASE-TX half duplex ability.

Always 1, since STE10/100A has 100BASE-TX

half duplex ability.

1RO

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