STE10A datasheet(35/82 Pages) STMICROELECTRONICS

35 / 82 page

STE10/100A

Registers and descriptors description

35/82

31~10

BRBA

Boot ROM base address. This value indicates the

address mapping of the boot ROM field as well as

defining the boot ROM size. The values of bit 16~10

are set to 0 indicating that the STE10/100A supports

up to 128Kbit of boot ROM.

X: b31~17

0: b16~10

R/W

9 ~ 1

---

Reserved

RO R/W

R/W

0BRE

Boot ROM enable. The STE10/100A will only enable

its boot ROM access if both the memory space

access bit (bit 1 of CR1) and this bit are set to 1.

1: enable boot ROM. (If bit 1 of CR1 is also set).

0R/W

CR13 (offset = 34h), CP - Capabilities pointer

31~8

---

Reserved

7~0

Capabilities pointer

C0h

CR15 (offset = 3ch), CI - Configuration interrupt

31~24

Max_Lat register. This value indicates how often the

STE10/100A needs to access to the PCI bus in units

of 250ns. This value is loaded from serial EEPROM

as a result of power-on or hardware reset.

From

EEPROM

23~16

Min_Gnt register. This value indicates how long the

STE10/100A needs to retain the PCI bus ownership

whenever it initiates a transaction, in units of 250ns.

This value is loaded from serial EEPROM as a result

power-on or hardware reset.

From

EEPROM

15~ 8

Interrupt Pin. This value indicates one of four

interrupt request pins to which the STE10/100A is

connected.

01h: means the STE10/100A always connects to

INTA#.

01h

7 ~ 0

Interrupt Line. This value indicates the system

interrupt request lines to which the INTA# of

STE10/100A is routed. The BIOS will fill this field

when it initializes and configures the system. The

STE10/100A driver can use this value to determine

priority and vector information.

0R/W

CR16 (offset = 40h), DS - Driver space for special purpose

31~16

---

Reserved

15~8

Driver space for implementation-specific purpose.

Since this area won’t be cleared upon software

reset, an STE10/100A driver can use this R/W area

as user-specified storage.

0R/W

7 ~ 0

---

Reserved

CR32 (offset = 80h), SIG - Signature of STE10/100A

Table 6.

Configuration registers description (continued)

Bit #

Name

Description

Default

RW type

STE10A Datasheet(PDF) 35 Page - STMicroelectronics

STE10A Datasheet(HTML) 35 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

Datasheet Download

Link URL