STE10A datasheet(44/82 Pages) STMICROELECTRONICS

44 / 82 page

Registers and descriptors description

STE10/100A

44/82

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Reserved

3TJT

Transmit jabber timer time-out.

1: when the transmit jabber timer expires. The

transmit processor will enter the stop state and

TO (bit 14 of TDES0, transmit jabber time-out

flag) will be asserted.

0RO/LH*

2TDU

Transmit descriptor unavailable.

1: when the next transmit descriptor can not be

obtained by the STE10/100A. The transmission

process is suspended in this situation. To restart

the transmission process, the ownership bit of

the next transmit descriptor should be set to

STE10/100A and, if the transmit automatic

polling is not enabled, a transmit poll demand

command should then be issued.

0RO/LH*

1TPS

Transmit process stopped.

1: while transmit state = stop

0RO/LH*

0TCI

Transmit completed interrupt.

1: set when a frame transmission completes with

IC (bit 31 of TDES1) asserted in the first transmit

descriptor of the frame.

0RO/LH*

LH = High Latching and cleared by writing 1.

CSR6 (offset = 30h), NAR - Network access register

31~22

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Reserved

Store and forward for transmit

0: disable

1: enable, ignore the transmit threshold setting

0R/W*

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Reserved

SQE

SQE disable

0: enable SQE function for 10BASE-T operation.

The STE10/100A provides SQE test function for

10BASE-T half duplex operation.

1: disable SQE function.

1R/W*

18~16

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Reserved

15~14

Transmit threshold control

00: 128-bytes (100Mbps), 72-bytes (10Mbps)

01: 256-bytes (100Mbps), 96-bytes (10Mbps)

10: 512-bytes (100Mbps), 128-bytes (10Mbps)

11: 1024-bytes (100Mbps), 160-bytes (10Mbps)

R/W*

Stop transmit

0: stop (default)

1: start

0R/W

Table 8.

Control/status register description (continued)

Bit #

Name

Description

Default

RW type

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