STE10A datasheet(43/82 Pages) STMICROELECTRONICS

43 / 82 page

STE10/100A

Registers and descriptors description

43/82

AISS

Abnormal interrupt status summary. Set if any of

the following bits of CSR5 are asserted:

–

TPS, transmit process stopped (bit 1)

–

TJT, transmit jabber timer time-out (bit

–

TUF, transmit under-flow (bit 5)

–

RDU, receive descriptor unavailable

(bit 7)

–

RPS, receive process stopped (bit 8)

–

RWT, receive watchdog time-out (bit

–

GPTT, general purpose timer time-out

(bit 11)

–

FBE, fatal bus error (bit 13)

0RO/LH*

----

Reserved

FBE

Fatal bus error.

1: on occurrence of parity error, master abort, or

target abort (see bits 25~23 of CSR5). The

STE10/100A will disable all bus access. A

software reset is required to recover from a

parity error.

0RO/LH*

---

Reserved

GPTT

General purpose timer timeout, based on

CSR11 timer register

0RO/LH*

---

Reserved

9RWT

Receive watchdog timeout, based on CSR15

watchdog timer register

0RO/LH*

RPS

Receive process stopped, receive state = stop

RO/LH*

RDU

Receive descriptor unavailable.

1: when the next receive descriptor can not be

obtained by the STE10/100A. The receive

process is suspended in this situation. To restart

the receive process, the ownership bit of the next

receive descriptor should be set to STE10/100A

and a receive poll demand command should be

issued (if the receive poll demand is not issued,

the receive process will resume when a new

recognized frame is received).

0RO/LH*

RCI

Receive completed interrupt.

1: when a frame reception is completed.

0RO/LH*

5TUF

Transmit under-flow.

1: when an under-flow condition occurs in the

transmit FIFO during transmitting. The transmit

process will enter the suspended state and

report the under-flow error on bit 1 of TDES0.

0RO/LH*

Table 8.

Control/status register description (continued)

Bit #

Name

Description

Default

RW type

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