ADFS7124-4BBCPZ datasheet(49/93 Pages) AD

49 / 93 page

Data Sheet

ADFS7124-4

ADC CIRCUIT INFORMATION

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Rev. 0 | 49 of 93

BRIDGE POWER-DOWN SWITCH

In bridge applications such as strain gages and load cells, the

bridge itself consumes the majority of the current in the system. For

example, a 350 Ω load cell requires 8.6 mA of current when excited

with a 3 V supply. To minimize the current consumption of the

system, the bridge can be disconnected (when it is not being used)

using the bridge power-down switch. The switch can withstand 30

mA of continuous current, and it has an on-resistance of 10 Ω

maximum. The PDSW bit in the IO_CONTROL_1 register controls

the switch.

LOGIC OUTPUTS

The ADFS7124-4 has two general-purpose digital outputs: P1 and

P2. These are enabled using the GPIO_CTRL bits in the IO_

CONTROL_1 register (see Table 50). The pins can be pulled high

or low using the GPIO_DATx bits in the register; that is, the value

at the pin is determined by the setting of the GPIO_DATx bits. The

logic levels for these pins are determined by AVDD rather than by

IOVDD.

These pins can be used to drive external circuitry, for example, an

external multiplexer. If an external multiplexer is used to increase

the channel count, the multiplexer logic pins can be controlled

through the ADFS7124-4 general-purpose output pins. The gener-

al-purpose output pins can be used to select the active multiplexer

pin. Because the operation of the multiplexer is independent of the

ADFS7124-4, reset the modulator and filter using the SYNC pin

or by writing to the mode or configuration register each time the

multiplexer channel is changed.

BIAS VOLTAGE GENERATOR

A bias voltage generator is included on the ADFS7124-4 (see

Figure 77). It biases the negative terminal of the selected input

channel to (AVDD − AVSS)/2. This function is useful in thermocouple

applications, as the voltage generated by the thermocouple must

be biased around some DC voltage if the ADC operates from a

single power supply. The bias voltage generator is controlled using

the VBIASx bits in the IO_CONTROL_2 register (see Table 52).

The power-up time of the bias voltage generator is dependent on

the load capacitance. Consult the Specifications section for more

details.

CLOCK

The ADFS7124-4 includes an internal 614.4 kHz clock on chip. This

internal clock has a tolerance of ±5%. Use either the internal clock

or an external clock as the clock source to the ADFS7124-4. The

clock source is selected using the CLK_SEL bits in the ADC_CON-

TROL register (see Table 53).

The internal clock can also be made available at the CLK pin. This

is useful when several ADCs are used in an application and the

devices must be synchronized. The internal clock from one device

can be used as the clock source for all ADCs in the system. Using

a common clock, the devices can be synchronized by applying a

common reset to all devices, or the SYNC pin can be pulsed.

POWER MODES

The ADFS7124-4 has three power modes: full power mode, mid

power mode, and low power mode. The mode is selected using the

POWER_MODE bits in the ADC_CONTROL register. The power

mode affects the power consumption of the device as well as

changing the controller clock frequency. A 614.4 kHz clock is used

by the device. However, this clock is internally divided, the division

factor being dependent on the power mode. Thus, the range of

output data rates and performance is affected by the power mode.

Table 51. Power Modes

Power Mode

Controller Clock

(kHz)

Output Data Rate1

(SPS)

Current

Full Power

614.4

9.37 to 19,200

See the

Specifications

section

Mid Power

153.6

2.34 to 4800

Low Power

76.8

1.17 to 2400

1 Unsettled, using a sinc3/sinc4 filter.

STANDBY AND POWER-DOWN MODES

In the standby mode, most blocks are powered down. The LDOs

remain active so that registers maintain their contents. If enabled,

the reference, internal oscillator, P1 and P2 digital outputs, bias

voltage generator, and low-side power switch remain active. The

excitation currents, if enabled, also remain active in the standby

mode. These blocks can be disabled, if required, by setting the

corresponding bits appropriately. The reference detection and LDO

capacitor detection functions are disabled in the standby mode.

Table 52. Input/Output Control 2 Register

Reg.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x04

IO_CONTROL_2

VBIAS7

VBIAS6

VBIAS5

VBIAS4

0x0000

VBIAS3

VBIAS2

VBIAS1

VBIAS0

Table 53. ADC Control Register

Reg.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x01

ADC_CONTROL

DOUT_RDY_DEL

CONT_READ

DATA_STATUS

CS_EN

REF_EN

0x0000

POWER_MODE

Mode

CLK_SEL

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