ADFS7124-4BBCPZ datasheet(90/93 Pages) AD

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Data Sheet

ADFS7124-4

ON-CHIP REGISTERS

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Rev. 0 | 90 of 93

Table 73. Channel Register Bit Descriptions (Continued)

Bits

Bit Name

Description

11110 = reserved.

11111 = reserved.

CONFIGURATION REGISTERS

RS[5:0] = 0, 1, 1, 0, 0, 1 to 1, 0, 0, 0, 0, 0

Power-On/Reset = 0x0860

The ADFS7124-4 has eight configuration registers, CONFIG_0 to CONFIG_7. Each configuration register is associated with a setup;

CONFIG_x is associated with Setup x. In the configuration register, the reference source, polarity, and reference buffers are configured. Table

74 outlines the bit designations for the register. Bit 15 is the first bit of the data stream. The number in parentheses indicates the power-on/reset

default status of that bit.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0 (0)

Bipolar (1)

Burnout (0)

REF_BUFP (0)

REF_BUFM (0)

AIN_BUFP (1)

AIN_BUFM (1)

REF_SEL (0)

PGA (0)

Table 74. Configuration Register Bit Descriptions

Bits

Bit Name

Description

15:12

These bits must be programmed with a Logic 0 for correct operation.

Bipolar

Polarity select bit. When this bit is set, bipolar operation is selected. When this bit is cleared, unipolar operation is selected.

10:9

Burnout

These bits select the magnitude of the sensor burnout detect current source.

00 = burnout current source off (default).

01 = burnout current source on, 0.5 μA.

10 = burnout current source on, 2 μA.

11 = burnout current source on, 4 μA.

REF_BUFP

Buffer enable on REFINx(+). When this bit is set, the positive reference input (internal or external) is buffered. When this bit is cleared, the positive

reference input (internal or external) is unbuffered.

REF_BUFM

Buffer enable on REFINx(−). When this bit is set, the negative reference input (internal or external) is buffered. When this bit is cleared, the

negative reference input (internal or external) is unbuffered.

AIN_BUFP

Buffer enable on AINP. When this bit is set, the selected positive analog input pin is buffered. When this bit is cleared, the selected positive analog

input pin is unbuffered.

AIN_BUFM

Buffer enable on AINM. When this bit is set, the selected negative analog input pin is buffered. When this bit is cleared, the selected negative

analog input pin is unbuffered.

4:3

REF_SEL

Reference source select bits. These bits select the reference source to use when converting on any channels using this configuration register.

00 = REFIN1(+)/REFIN1(−).

01 = REFIN2(+)/REFIN2(−).

10 = internal reference.

11 = AVDD.

2:0

PGA

Gain select bits. These bits select the gain to use when converting on any channels using this configuration register.

PGA

Gain

Input Range When VREF = 2.5 V (Bipolar Mode)

000

±2.5 V

001

±1.25 V

010

± 625 mV

011

±312.5 mV

100

±156.25 mV

101

±78.125 mV

110

±39.06 mV

111

128

±19.53 mV

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