ADFS7124-4BBCPZ datasheet(83/93 Pages) AD

83 / 93 page

Data Sheet

ADFS7124-4

ON-CHIP REGISTERS

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Rev. 0 | 83 of 93

Table 67. Operating Modes (Continued)

Mode Value Description

full-scale error. Select only one channel when full-scale calibration is being performed. The ADFS7124-4 is factory calibrated at a gain of 1. Further internal

full-scale calibrations at a gain of 1 are not supported. An internal full-scale calibration (gain > 1) takes a time of four settling periods.

Internal full-scale calibrations cannot be performed in the full power mode. So, if using the full-power mode, select mid or low power mode for the internal

full-scale calibration. This calibration is valid in the full power mode as the same reference and gain are used. When performing internal zero-scale and internal

full-scale calibrations, the internal full-scale calibration must be performed before the internal zero-scale calibration. Therefore, write 0x800000 to the offset

0111

System zero-scale (offset) calibration. Connect the system zero-scale input to the channel input pins of the selected channel. RDY goes high when the

calibration is initiated and returns low when the calibration is complete. The ADC is placed in the idle mode following a calibration. The measured offset

coefficient is placed in the offset register of the selected channel. A system zero-scale calibration is required each time the gain of a channel is changed. Select

only one channel when full-scale calibration is being performed. A system zero-scale calibration takes a time of one settling period to be performed.

1000

System full-scale (gain) calibration. Connect the system full-scale input to the channel input pins of the selected channel. RDY goes high when the calibration

is initiated and returns low when the calibration is complete. The ADC is placed in the idle mode following a calibration. The measured full-scale coefficient is

placed in the gain register of the selected channel. A full-scale calibration is required each time the gain of a channel is changed. Select only one channel when

full-scale calibration is being performed. A system full-scale calibration takes a time of one settling period to be performed.

1001 to1111 Reserved.

DATA REGISTER

RS[5:0] = 0, 0, 0, 0, 1, 0

Power-On/Reset = 0x000000

The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from this

IO_CONTROL_1 REGISTER

RS[5:0] = 0, 0, 0, 0, 1, 1 Power-On/Reset = 0x000000

Table 68 outlines the bit designations for the register. Bit 23 is the first bit of the data stream. The number in parentheses indicates the

power-on/reset default status of that bit.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

GPIO_DAT2 (0)

GPIO_DAT1 (0)

0 (0)

GPIO_CTRL2 (0)

GPIO_CTRL1 (0)

0 (0)

PDSW (0)

0 (0)

IOUT1 (0)

IOUT0 (0)

IOUT1_CH (0)

IOUT0_CH (0)

Table 68. IO_CONTROL_1 Register Bit Descriptions

Bits

Bit Name

Description

GPIO_DAT2

Digital Output P2. When GPIO_CTRL2 is set, the GPIO_DAT2 bit sets the value of the P2 general-purpose output pin. When

GPIO_DAT2 is high, the P2 output pin is high. When GPIO_DAT2 is low, the P2 output pin is low.

GPIO_DAT1

Digital Output P1. When GPIO_CTRL1 is set, the GPIO_DAT1 bit sets the value of the P1 general-purpose output pin. When

GPIO_DAT1 is high, the P1 output pin is high. When GPIO_DAT1 is low, the P1 output pin is low.

21, 20

This bit must be programmed with a Logic 0 for correct operation.

GPIO_CTRL2

Digital Output P2 enable. When GPIO_CTRL2 is set, the digital output P2 is active. When GPIO_CTRL2 is cleared, the pin

functions as an analog input, AIN3.

GPIO_CTRL1

Digital Output P1 enable. When GPIO_CTRL1 is set, the digital output P1 is active. When GPIO_CTRL1 is cleared, the pin

functions as an analog input, AIN2.

17, 16

This bit must be programmed with a Logic 0 for correct operation.

PDSW

Bridge power-down switch control bit. Set this bit to close the bridge power-down switch PDSW to AGND. The switch can sink up

to 30 mA. Clear this bit to open the bridge power-down switch. When the ADC is placed in standby mode, the bridge power-down

switch remains active.

This bit must be programmed with a Logic 0 for correct operation.

13:11

IOUT1

These bits set the value of the excitation current for IOUT1.

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