ADFS7124-4BBCPZ datasheet(15/93 Pages) AD

15 / 93 page

Data Sheet

ADFS7124-4

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

analog.com

Rev. 0 | 15 of 93

Table 6. Pin Function Descriptions (Continued)

Pin No.

Mnemonic

Description

Alternatively, the internal programmable excitation current source can be made available at this pin. Either

IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply rails

can be generated at this pin.

AIN6/IOUT/VBIAS/

REFIN2(+)

Analog Input 6/Output of Internal Excitation Current Source/Bias Voltage/Positive Reference Input. This input

pin is configured through the configuration registers to be the positive or negative terminal of a differential

or pseudodifferential input. Alternatively, the internal programmable excitation current source can be made

available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between

the analog power supply rails can be generated at this pin. This pin also functions as a positive reference input

for REFIN2(±). REFIN2(+) can be anywhere between AVDD and AVSS + 0.5 V. The nominal reference voltage

(REFIN2(+) to REFIN2(−)) is 2.5 V, but the device functions with a reference from 0.5 V to AVDD.

AIN7/IOUT/VBIAS/

REFIN2(−)

Analog Input 7/Output of Internal Excitation Current Source/Bias Voltage/Negative Reference Input. This input

pin is configured through the configuration registers to be the positive or negative terminal of a differential or

pseudodifferential input. Alternatively, the internal programmable excitation current source can be made available

at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog

power supply rails can be generated at this pin. This pin also functions as the negative reference input for

REFIN2(±). This reference input can be anywhere between AVSS and AVDD – 0.5 V.

REFOUT

Internal Reference Output. The buffered output of the internal 2.5 V voltage reference is available on this pin.

AVSS

Analog Supply Voltage. The voltage on AVDD is referenced to AVSS. The differential between AVDD and AVSS

must be between 2.7 V and 3.6 V in mid or low power mode and between 2.9 V and 3.6 V in full power mode.

AVSS can be taken below 0 V to provide a dual power supply to the ADFS7124-4. For example, AVSS can be tied

to −1.8 V and AVDD can be tied to +1.8 V, providing a ±1.8 V supply to the ADC.

REGCAPA

Analog LDO Regulator Output. Decouple this pin to AVSS with a 0.1 µF capacitor.

PSW

Low-Side Power Switch to AVSS.

AVDD

Analog Supply Voltage, Relative to AVSS.

SYNC

Synchronization Input. This pin is a logic input that allows synchronization of the digital filters and analog

modulators when using a number of ADFS7124-4 devices. When SYNC is low, the nodes of the digital filter, the

filter control logic, and the calibration control logic are reset, and the analog modulator is held in a reset state.

SYNC does not affect the digital interface but does reset RDY to a high state if it is low.

DOUT/RDY

Serial Data Output/Data Ready Output. DOUT/RDY functions as a serial data output pin to access the output

shift register of the ADC. The output shift register can contain data from any of the on-chip data or control

registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a

conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The

DOUT/RDY falling edge can also be used as an interrupt to a processor, indicating that valid data is available.

With an external serial clock, the data can be read using the DOUT/RDY pin. When CS is low, the data/control

word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge.

DIN

Serial Data Input to the Input Shift Register on the ADC. Data in the input shift register is transferred to the

control registers within the ADC, with the register selection bits of the communications register identifying the

appropriate register.

SCLK

Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK pin has a

Schmitt-triggered input, making the interface suitable for opto-isolated applications. The serial clock can be

continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock

with the information being transmitted to or from the ADC in smaller batches of data.

CLK

Clock Input/Clock Output. The internal clock can be made available at this pin. Alternatively, the internal clock

can be disabled, and the ADC can be driven by an external clock. This allows several ADCs to be driven from a

common clock, allowing simultaneous conversions to be performed.

Chip Select Input. This is an active low logic input that selects the ADC. Use CS to select the ADC in systems

with more than one device on the serial bus or as a frame synchronization signal in communicating with the

device. CS can be hardwired low if the serial-peripheral interface (SPI) diagnostics are unused, allowing the ADC

to operate in 3-wire mode with SCLK, DIN, and DOUT interfacing with the device.

Exposed Pad. Connect the exposed pad to AVSS.

ADFS7124-4BBCPZ Datasheet(PDF) 15 Page - Analog Devices

ADFS7124-4BBCPZ Datasheet(HTML) 15 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93

Datasheet Download

Link URL