©2015-2018

DS20005008C

18

64 Mbit Multi-Purpose Flash Plus

SST39VF6401B / SST39VF6402B

Not Recommended for New Designs

AC Characteristics

Table 16: Read Cycle Timing Parameters VDD = 2.7-3.6V

Symbol

Parameter

SST39VF640xB-70

Units

Min

Max

TRC

Read Cycle Time

70

ns

TCE

Chip Enable Access Time

70

ns

TAA

Address Access Time

70

ns

TOE

Output Enable Access Time

35

ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

CE# Low to Active Output

0

ns

TOLZ1

OE# Low to Active Output

0

ns

TCHZ1

CE# High to High-Z Output

20

ns

TOHZ1

OE# High to High-Z Output

20

ns

TOH1

Output Hold from Address Change

0

ns

TRP1

RST# Pulse Width

500

ns

TRHR1

RST# High before Read

50

ns

TRY1,2

2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.

This parameter does not apply to Chip-Erase operations.

RST# Pin Low to Read Mode

20

µs

T16.0 25008

Table 17: Program/Erase Cycle Timing Parameters

Symbol

Parameter

Min

Max

Units

TBP

Word-Program Time

10

µs

TAS

Address Setup Time

0

ns

TAH

Address Hold Time

30

ns

TCS

WE# and CE# Setup Time

0

ns

TCH

WE# and CE# Hold Time

0

ns

TOES

OE# High Setup Time

0

ns

TOEH

OE# High Hold Time

10

ns

TCP

CE# Pulse Width

40

ns

TWP

WE# Pulse Width

40

ns

TWPH1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

WE# Pulse Width High

30

ns

TCPH1

CE# Pulse Width High

30

ns

TDS

Data Setup Time

30

ns

TDH1

Data Hold Time

0

ns

TIDA1

Software ID Access and Exit Time

150

ns

TSE

Sector-Erase

25

ms

TBE

Block-Erase

25

ms

TSCE

Chip-Erase

50

ms

T17.0 25008