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SST39VF6401B Datasheet(PDF) 21 Page - Microchip Technology |
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SST39VF6401B Datasheet(HTML) 21 Page - Microchip Technology |
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21 / 38 page ![]() ©2015-2018 DS20005008C 21 64 Mbit Multi-Purpose Flash Plus SST39VF6401B / SST39VF6402B Not Recommended for New Designs Figure 8: Toggle Bits Timing Diagram Figure 9: WE# Controlled Chip-Erase Timing Diagram 1288 F07.0 ADDRESS AMS-0 DQ6 and DQ2 WE# OE# CE# TOE TOEH TCE TOES TWO READ CYCLES WITH SAME OUTPUTS Note: AMS = Most significant address AMS = A21 for SST39VF640xB 1288 F08.0 ADDRESS AMS-0 DQ15-0 WE# SW0 SW1 SW2 SW3 SW4 SW5 555 2AA 2AA 555 555 XX55 XX10 XX55 XXAA XX80 XXAA 555 OE# CE# SIX-BYTE CODE FOR CHIP-ERASE TSCE TWP Note: This device also supports CE# controlled Chip-Erase operation The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 17) AMS = Most significant address AMS = A21 for SST39VF640xB WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence. X can be VIL or VIH, but no other value. |
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