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WM9713LGEFL/V Datasheet(PDF) 38 Page - Wolfson Microelectronics plc |
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WM9713LGEFL/V Datasheet(HTML) 38 Page - Wolfson Microelectronics plc |
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38 / 108 page  WM9713L Pre-Production w PP Rev 3.0 June 2006 38 VARIABLE RATE AUDIO / SAMPLE RATE CONVERSION By using an AC’97 Rev2.2 compliant audio interface, the WM9713L can record and playback at all commonly used audio sample rates, and offer full split-rate support (i.e. the DAC, ADC and AUXDAC sample rates are completely independent of each other – any combination is possible). The default sample rate is 48kHz. If the VRA bit in register 2Ah is set, then other sample rates can be selected by writing to registers 2Ch, 32h and 2Eh. The AC-Link continues to run at 48k frames per second irrespective of the sample rate selected. However, if the sample rate is less than 48kHz, then some frames do not carry an audio sample. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 2Ah Extended Audio Stat/Ctrl 0 VRA 0 (OFF) Variable Rate Audio 0: OFF (DAC and ADC run at 48kHz) 1: ON (sample rates determined by registers 2Ch and 32h) 2Ch Audio DAC Sample Rate 15:0 DACSR BB80h (48kHz) Audio DAC sample rate 1F40h: 8kHz 2B11h: 11.025kHz 2EE0h: 12kHz 3E80h: 16kHz 5622h: 22.05kHz 5DC0h: 24kHz 7D00h: 32kHz AC44h: 44.1kHz BB80h: 48kHz Any other value defaults to the nearest supported sample rate 32h Audio ADC Sample Rate 15:0 ADCSR BB80h (48kHz) Audio ADC sample rate similar to DACSR 2Eh AUXDAC Sample Rate 15:0 AUXDA CSR BB80h (48kHz) AUXDAC sample rate similar to DACSR Table 21 Audio Sample Rate Control Note: Changing the ADC and / or DAC sample rate will only be effective if the ADC’s and DAC’s are enabled and powered up before the sample rate is changed. This is done by setting the relevant bits in registers 26h and 3Ch, as well as the VRA bit in register 2Ah. The process is as follows: 1. Enable and power up ADC’s and or DAC’s in registers 26h and 3Ch. 2. Enable VRA bit in 2Ah, bit 0. 3. Change the sample rate in the respective register. |
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