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WM9713LGEFL/V Datasheet(PDF) 82 Page - Wolfson Microelectronics plc |
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WM9713LGEFL/V Datasheet(HTML) 82 Page - Wolfson Microelectronics plc |
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82 / 108 page  WM9713L Pre-Production w PP Rev 3.0 June 2006 82 PARAMETER SYMBOL MIN TYP MAX UNIT BITCLK frequency 12.288 MHz BITCLK period tCLK_PERIOD 81.4 ns BITCLK output jitter 750 ps BITCLK high pulse width (Note 1) tCLK_HIGH 36 40.7 45 ns BITCLK low pulse width (Note 1) tCLK_LOW 36 40.7 45 ns SYNC frequency 48 kHz SYNC period tSYNC_PERIOD 20.8 µs SYNC high pulse width tSYNC_HIGH 1.3 µs SYNC low pulse width tSYNC_LOW 19.5 µs Note: 1. Worst case duty cycle restricted to 45/55 DATA SETUP AND HOLD Figure 29 Data Setup and Hold (50pF External Load) Note: Setup and hold times for SDATAIN are with respect to the AC’97 controller, not the WM9713L. PARAMETER SYMBOL MIN TYP MAX UNIT Setup to falling edge of BITCLK tSETUP 10 ns Hold from falling edge of BITCLK tHOLD 10 Ns Output valid delay from rising edge of BITCLK tCO 15 ns |
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