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WM9713LGEFL/V Datasheet(PDF) 84 Page - Wolfson Microelectronics plc |
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WM9713LGEFL/V Datasheet(HTML) 84 Page - Wolfson Microelectronics plc |
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84 / 108 page ![]() WM9713L Pre-Production w PP Rev 3.0 June 2006 84 COLD RESET (ASYNCHRONOUS, RESETS REGISTER SETTINGS) RESETB BITCLK t RST_LOW t RST2CLK Figure 32 Cold Reset Timing Note: For correct operation SDATAOUT and SYNC must be held LOW for entire RESETB active low period otherwise the device may enter test mode. See AC'97 specification or Wolfson applications note WAN104 for more details. PARAMETER SYMBOL MIN TYP MAX UNIT RESETB active low pulse width tRST_LOW 1.0 µs RESETB inactive to BITCLK startup delay tRST2CLK 162.8 ns WARM RESET (ASYNCHRONOUS, PRESERVES REGISTER SETTINGS) Figure 33 Warm Reset Timing PARAMETER SYMBOL MIN TYP MAX UNIT SYNC active high pulse width tSYNC_HIGH 1.3 µs SYNC inactive to BITCLK startup delay tRST2CLK 162.4 ns |
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