WM9713LGEFLSLASHV datasheet(19/108 Pages) WOLFSON

19 / 108 page

Pre-Production

WM9713L

PP Rev 3.0 June 2006

PLL REGISTER PAGE ADDRESS MAPPING

The clock division control bits SPLL[6:0] and the PLL fractional N division bits are accessed through

words to be accessed whilst the register address is set to 46h. This means that when register

address 46h is selected a further 7 cycles of programming are required to set all of the page data

bits. Control bit allocation for these page addresses is described in Table 6.

PAGE

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

111

31:28

SPLL[6:4]

110

27:24

SPLL[3:0]

Clock division control bus SPLL[6:0]. Clock

divider reads this control word if PLL is

enabled. Bits [6:4] and [3:0] have the same

functionality as

44h [14:12] and [11:8]

respectively

23:22

Reserved

Reserved bits

101

21:20

100

19:16

011

15:12

010

11:8

001

7:4

000

3:0

K[21:0]

Sigma Delta Modulator control word for

fractional N division. Division resolution is

1/22

Table 6 Pager Control Bit Allocation

Powerdown for the PLL and internal clocks is via registers 26h and 3Ch (see Table 7).

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

26h

PR5

1 (Off)

Internal clock disable (active high)

3Ch

PLL

1 (Off)

PLL powerdown (active high)

N.B. both PR5 and PLL must be asserted low before PLL is enabled

Table 7 PLL Powerdown Control

DIGITAL INTERFACES

The WM9713L has two interfaces, a data and control AC’97 interface and a data only PCM interface.

The AC’97 interface is available through dedicated pins (SDATAOUT, SDATAIN, SYNC, BITCLK and

RESETB) and is the sole control interface with access to all data streams on the device except for

the Voice DAC. The PCM interface is available through the GPIO pins (PCMCLK, PCMFS, PCMDAC

and PCMADC) and provides access to the Voice DAC. It can also transmit the data from the Stereo

ADC. This can be useful, for example, to allow both sides of a phone conversation to be recorded by

mixing the transmit and receive paths on one of the ADC channels and transmitting it over the PCM

interface.

AC97 INTERFACE

INTERFACE PROTOCOL

The WM9713L uses an AC’97 interface for both data transfer and control. The AC-Link has 5 wires:

•

SDATAIN (pin 8) carries data from the WM9713L to the controller

•

SDATAOUT (pin 5) carries data from the controller to the WM9713L

•

BITCLK (pin 6) is a clock, derived from either MCLKA or MCLKB inputs and

supplied to the controller.

•

SYNC is a synchronization signal generated by the controller and passed to the

WM9713L

•

RESETB resets the WM9713L to its default state

WM9713LGEFL/V Datasheet(PDF) 19 Page - Wolfson Microelectronics plc

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