T89C51RB2-3CSIM datasheet(97/117 Pages) ATMEL

97 / 117 page

T89C51RB2/RC2

4105D–8051–10/06

Table 72. Default Values

After programming the part by ISP, the BSB must be cleared (00h) in order to allow the

application to boot at 0000h.

The content of the Software Security Byte (SSB) is described in Table 72 and Table 74.

To assure code protection from a parallel access, the HSB must also be at the required

level.

Table 73. Software Security Byte

The two lock bits provide different levels of protection for the on-chip code and data,

when programmed as shown to Table 74.

Mnemonic

Definition

Default value

Description

SBV

Software Boot Vector

FCh

HSB

Copy of the Hardware security byte

101x 1011b

BSB

Boot Status Byte

0FFh

SSB

Software Security Byte

FFh

Copy of the Manufacturer Code

58h

ATMEL

Copy of the Device ID #1: Family Code

D7h

C51 X2, Electrically Erasable

Copy of the Device ID #2: memories

F7h

T89C51RB2/RC2 32KB

size and type

FBh

T89C51RB2/RC2 16 KB

Copy of the Device ID #3: name and

revision

EFh

T89C51RB2/RC2 32KB,

Revision 0

FFh

T89C51RB2/RC2 16 KB,

Revision 0

---

LB1

LB0

Bit

Number

Bit

Mnemonic

Description

Reserved

Do not clear this bit.

Reserved

Do not clear this bit.

Reserved

Do not clear this bit.

Reserved

Do not clear this bit.

Reserved

Do not clear this bit.

Reserved

Do not clear this bit.

1-0

LB1-0

User Memory Lock Bits

See Table 74

T89C51RB2-3CSIM Datasheet(PDF) 97 Page - ATMEL Corporation

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