MPF5020CMBA0ES datasheet(21/106 Pages) NXP

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NXP Semiconductors

PF5020

Power management integrated circuit (PMIC) for high performance applications

When the VIN_OVLO_EN = 0, the OVLO monitor is disabled and when the VIN_OVLO_EN = 1, the OVLO

monitor is enabled. The default configuration of the VIN_OVLO_EN bit is set by the OTP_VIN_OVLO_EN bit

in OTP. Likewise, the default value of the VIN_OVLO_SDWN bit is set by the OTP_VIN_OVLO_SDWN upon

power up.

During a power up transition, if the OTP_VIN_OVLO_SDWN = 0 the device allows the external

regulators to come up and the PF5020 announces the VIN_OVLO condition through an interrupt. If the

OTP_VIN_OVLO_SDWN = 1, the device stops the power up sequence and returns to the corresponding Off

mode.

Debounce on the VIN_OVLO comparator is programmable to 10 µs, 100 µs or 1.0 ms, by

the VIN_OVLO_DBNC[1:0] bits. The default value for the VIN_OVLO debounce is set by the

OTP_VIN_OVLO_DBNC[1:0] bits upon power up.

VIN_OVLO_DBNC[1:0]

VIN OVLO debounce value (µs)

100

1000

Reserved

Table 13. VIN_OVLO debounce configuration

Symbol

Parameter

Min

Typ

Max

Unit

VIN_OVLO

VIN overvoltage lockout rising

[1] 5.6

5.8

6.0

VIN_OVLO_HYS

VIN overvoltage lockout hysteresis

[1] —

—

200

Table 14. VIN_OVLO specifications

[1]

Operating the device above the maximum VIN = 5.5 V for extended period of time may degrade and cause permanent damage to the device.

14.3 IC startup timing with PWRON pulled up

The PF5020 features a fast internal core power up sequence to fulfill system power up timings of 5.0 ms or less,

from power application until MCU is out of reset. Such requirement needs a maximum ramp up time of 1.5 ms

for VIN to cross the UVDET threshold in the rising edge.

A maximum core biasing time of 1.5 ms from VIN crossing to UVDET until the beginning of the power up

sequence is ensured to allow up to 1.5 ms time frame for the voltage regulators power up sequence.

Timing for the external regulators to start up is programmed by default in the OTP fuses.

The 5.0 ms power up timing requirement is only applicable when the PWRON pin operates in level sensitive

mode OTP_PWRON_MODE = 0, however turn on timing is expected to be the same for both level or edge

sensitive modes after the power on event is present.

In applications using the VSNVS regulator, if VSNVS is required to reach regulation before system regulators

come up, the system should use the SEQ[7:0] bits to delay the system regulators to allow enough time for

VSNVS to reach regulation before the power up sequence is started.

PF5020

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.2 — 5 March 2024

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