MPF5020CMBA0ES datasheet(53/106 Pages) NXP

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NXP Semiconductors

PF5020

Power management integrated circuit (PMIC) for high performance applications

SWxILIM[1:0]

Typical current limit

2.1 A

2.6 A

3.0 A

4.5 A

Table 42. SWx current limit selection

The current limit specification is given with respect to the inductor peak current. To calculate the DC current

at which the buck regulator would enter into current limitation, it is necessary to calculate the inductor ripple

current. An ideal approximation is enough to obtain the ripple current as follows:

ΔiL = [(VIN-VOUT) × (VOUT/VIN)]/(L × FSW)

Where L is the inductance value and Fsw is the selected switching frequency.

The DC current limit is then calculated by

DC ILIM = ILIM - (ΔiL / 2)

In order to account for component tolerances, use the minimum inductor value per the inductor specification.

During single phase operation, all buck regulators use 3 bits (SWxPHASE[2:0]) to control the phase shift of the

switching frequency. Upon power up, the switching phase of all regulators is defaulted to 0 degrees and can be

modified during the system On state.

SWx_PHASE[2:0]

Phase shift [degrees]

000

001

010

135

011

180

100

225

101

270

110

315

111

0 (default)

Table 43. SWx phase configuration

Each one of the buck regulator provides 2 OTP bits to configure the value of the inductor used in the

corresponding block. The OTP_SWx_LSELECT[1:0] allows to choose the inductor as shown in Table 44.

OTP_SWx_LSELECT[1:0]

Inductor value

1.0 µH

0.47 µH

1.5 µH

Reserved

Table 44. SWx inductor selection bits

15.3.1 SW2 VTT operation

SW2 features a selectable VTT mode to create VTT termination for DDR memories.

When SW2_VTTEN = 1, the VTT mode is enabled. In this mode, SW2 reference voltage is internally connected

to SW1FB output through a divider by 2.

PF5020

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.2 — 5 March 2024

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