MPF5020CMBA0ES datasheet(78/106 Pages) NXP

78 / 106 page

NXP Semiconductors

PF5020

Power management integrated circuit (PMIC) for high performance applications

Bit name

Bits

LDO1_STBY_EN

LDO1 CONFIG2

LDO1_SEQ [7:0]

LDO1 PWRUP

7:0

VLDO1_RUN[3:0]

LDO1 RUN VOLT

3:0

VLDO1_STBY[3:0]

LDO1 STBY VOLT

3:0

Table 69. Soft WD register reset...continued

A soft WD reset may require all or some regulators to be reset to their default OTP configuration. In the event a

regulator is required to keep its current configuration during a soft WD reset, a watchdog bypass bit is provided

for each regulator (SWx_WDBYPASS / LDOx_WDBYPASS).

• When the WDBYPASS = 0, the watchdog bypass is disabled and the output of the corresponding regulator is

returned to its default OTP value during the soft WD reset.

• When the WDBYPASS = 1, the watchdog bypass is enabled and the output of the corresponding regulator is

not affected by the soft WD reset, keeping its current configuration.

During a soft WD reset, only regulators that are activated in the power up sequence go back to their default

voltage configuration if their corresponding WDBYPASS = 0.

Switching regulators returning to their default voltages configuration, will gradually reach the new output voltage

using its DVS configuration. LDO regulator returning to their default configuration, will change to the default

output voltage configuration instantaneously. Regulators with WDBYPASS = 0 and which are not activated

during the power up sequence will turn off immediately.

After all output voltages have transitioned to their corresponding default values, the device waits for at least 30

μs before returning to the Run state and announces it has finalized the soft WD reset by asserting the INTB pin,

provided the WDI_I interrupt is not masked.

aaa-028073

System

30 µs

WD Reset

Power Down

Sequence

Default OTP Configuration

INTB

RESETBMCU

VSNVS

In Power up

Sequence

Not in Power

up Sequence

Regulator with

WDBYPASS = 1

WDBYPASS = 0

WDI Event

Configuration Maintained

WDI OK

WDI Event

Soft WD Reset Behavior

Figure 32. Soft WD reset behavior

A hard WD reset is used to force a system power-on reset when the MCU has become unresponsive. In this

scenario, a full OTP register reset is performed.

PF5020

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.2 — 5 March 2024

78 / 106

MPF5020CMBA0ES Datasheet(PDF) 78 Page - NXP Semiconductors

MPF5020CMBA0ES Datasheet(HTML) 78 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL